31.9.2 PWMxCLK
| Name: | PWMxCLK |
| Offset: | 0x461,0x470,0x47F,0x48E |
PWMx Clock Source
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLK[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 4:0 – CLK[4:0] PWM Clock Source Select
| CLK | Source | Operates in Sleep |
|---|---|---|
11111-10110 |
Reserved | N/A |
10100 |
CLC8_OUT | Yes(1) |
10011 |
CLC7_OUT | Yes(1) |
10010 |
CLC6_OUT | Yes(1) |
10001 |
CLC5_OUT | Yes(1) |
10000 |
CLC4_OUT | Yes(1) |
01111 |
CLC3_OUT | Yes(1) |
01110 |
CLC2_OUT | Yes(1) |
01101 |
CLC1_OUT | Yes(1) |
01100 |
NCO3_OUT | Yes(1) |
01011 |
NCO2_OUT | Yes(1) |
01010 |
NCO1_OUT | Yes(1) |
01001 |
CLKREF | Yes(1) |
01000 |
EXTOSC | Yes |
00111 |
SOSC | Yes |
00110 |
MFINTOSC (32 kHz) | Yes |
00101 |
MFINTOSC (500 kHz) | Yes |
00100 |
LFINTOSC | Yes |
00011 |
HFINTOSC | Yes |
00010 |
FOSC | No |
00001 |
PWMIN1PPS | Yes(1) |
00000 |
PWMIN0PPS | Yes(1) |
|
Note: Operation
during Sleep is possible if the clock supplying the source
peripheral operates in Sleep.
|
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