31.9.12 PWMxSaP2
Note: The individual bytes in this multibyte
register can be accessed with the following register names:
- PWMxSaP2H: Accesses the high byte P2[15:8]
- PWMxSaP2L: Accesses the low byte P2[7:0]
Name: | PWMxSaP2 |
PWM Slice “a” Parameter 2 Register
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
P2[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
P2[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:0 – P2[15:0] Parameter 2 Value
Value | Name | Description |
---|---|---|
n | Compare | Compare match event occurs when PWMx timer = n (refer to MODE selections) |
n | Variable Aligned | PWMx_SaP1_out and PWMx_SaP2 both go low when PWMx timer = n |
n | Center-Aligned | PWMx_SaP2_out is high 2*n PWMx clock periods centered around PWMx period event |
n | Right Aligned | PWMx_SaP2_out is high n PWMx clock periods at end of PWMx period |
n | Left Aligned | PWMx_SaP2_out is high n PWMx clock periods at beginning of PWMx period |