35.8 Stop Bits
The number of Stop bits is user selectable with the STP bits. The STP bits affect all modes of operation.
Stop bits selections are shown in the table below:
| Transmitter Stop Bits | Receiver Verification |
|---|---|
| 1 | Verify Stop bit |
| 1.5 | Verify first Stop bit |
| 2 | Verify both Stop bits |
| 2 | Verify only first Stop bit |
In all modes, except DALI, the transmitter is Idle for the number of Stop bit periods between each consecutively transmitted word. In DALI, the Stop bits are generated after the last bit in the transmitted data stream.
The input is checked for the idle level in the middle of the first Stop bit, when receive verify on first is selected, as well as in the middle of the second Stop bit, when verify on both is selected. If any Stop bit verification indicates a nonidle level, the framing error FERIF bit is set for the received word.