43.7.6 ADCLK

ADC Clock divider Register
Note: ADC Clock divider is only available if FOSC is selected as the ADC clock source (CS = 0).
Name: ADCLK
Offset: 0x3FA

Bit 76543210 
   CS[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 5:0 – CS[5:0] ADC Clock divider Select

ValueDescription
n ADC Clock frequency = FOSC/(2*(n+1))
ADC Clock divider is only available if FOSC is selected as the ADC clock source (CSADC Clock Selection = 0).