Introduction

The High-Speed Serial Interface block in the SmartFusion2 and IGLOO2 families provides multiple high speed serial protocols, such as PCIe end-point and XAUI. In addition, it enables the FPGA fabric to connect with the External Physical Coding Sublayer (EPCS) Interface and implement any user-defined protocol in the fabric. The device might contain one or more High Speed Serial Interface blocks depending on the size. See the IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet.

Note: The document is intended for Libero SoC SERDES_IF core. For more details about the High Speed Serial Interface, see the UG0447: SmartFusion2 and IGLOO2 FPGA High-Speed Serial Interfaces User Guide.

Libero® SoC v2021.2

Introduction