Libero® SoC v2021.2

3 Port Description

This chapter includes the following sections:

APB Ports (APB Ports)
PCIe Ports (PCIe Ports)
PCIe AXI Master Ports (PCIe AXI Master Ports)
PCIe AXI Slave Ports (PCIe AXI Slave Ports)
PCIe AHBLite Master Ports (PCIe AHBLite Master Ports)
PCIe AHBLite Slave Ports (PCIe AHBLite Slave Ports)
XAUI Ports (XAUI Ports)
EPCS Ports per Lane (EPCS Ports per Lane)
PAD Ports (PAD Ports)

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.