| 1 | AVSS | Analog ground | 
| 2 | AVSS | Analog ground | 
| 3 | DEVDD | Digital power input pin | 
| 4 | DEVDD | Digital power input pin | 
| 5 | /RST | REST active low | 
| 6 | /SEL | SPI select, active low | 
| 7 | MOSI | SPI data input | 
| 8 | MISO | SPI data output | 
| 9 | SCLK | SPI clock | 
| 10 | DIG1 | Reserved | 
| 11 | FEM_CSD | Reserved | 
| 32 | DIG3 | RX-TX indication | 
| 33 | DIG4 | RX-TX indication (inverted) | 
| 34 | DIG2 | TX-RX timestamp | 
| 35 | SLP_TR | Controls sleep, deep sleep, transmit start, receive states; active high | 
| 36 | SCL | TWI- EEPROM | 
| 37 | SDA | TWI- EEPROM | 
| 38 | FEM_CPS | Front-end module select for RF_TX_RX | 
| 39 | CLKM | Master clock output | 
| 40 | IRQ | Interrupt request signal output | 
| 41 | DVSS | Digital ground | 
| 42 | DVSS | Digital ground |