2 Pin Descriptions

The descriptions of the pins are listed in Table 2-1.

Table 2-1. Pin Function Table
Name	32‑Lead CERDIP	32-Lead CLCC	32-Lead FLATPACK	30‑Pin PGA	Function
NC	1	1	1	—	No Connect
A16	2	2	2	30	Address
A15	3	3	3	29	Address
A12	4	4	4	2	Address
A7	5	5	5	3	Address
A6	6	6	6	4	Address
A5	7	7	7	5	Address
A4	8	8	8	6	Address
A3	9	9	9	7	Address
A2	10	10	10	8	Address
A1	11	11	11	9	Address
A0	12	12	12	10	Address
I/O0	13	13	13	11	Data Input/Output
I/O1	14	14	14	12	Data Input/Output
I/O2	15	15	15	13	Data Input/Output
GND	16	16	16	14	Ground
I/O3	17	17	17	15	Data Input/Output
I/O4	18	18	18	16	Data Input/Output
I/O5	19	19	19	17	Data Input/Output
I/O6	20	20	20	18	Data Input/Output
I/O7	21	21	21	19	Data Input/Output
CE	22	22	22	20	Chip Enable
A10	23	23	23	21	Address
OE	24	24	24	22	Output Enable
A11	25	25	25	23	Address
A9	26	26	26	24	Address
A8	27	27	27	25	Address
A13	28	28	28	26	Address
A14	29	29	29	1	Address
NC	30	30	30	—	No Connect
WE	31	31	31	27	Write Enable
V_CC	32	32	32	28	Device Power Supply