1 Silicon Issue Summary

Legend

-
Erratum is not applicable.
X
Erratum is applicable.
PeripheralShort DescriptionValid for Silicon Revision
Rev. A3(1)Rev. A4Rev. A7
Device Some Reserved Fuse Bits Are ‘1’ X--
CRC Check During Reset Initialization Is not Functional XX-
Write Operation Lost if Consecutive Writes to Specific Address Spaces XXX
ADC ADC MUX Selection and Accumulation Number has Delayed Update When Initialization Delay is Used XXX
CCL The LINK Input Source Selection for LUT3 Is not Functional on 28- and 32-Pin Devices XXX
CLKCTRL PLL Status not Working as Expected XXX
DAC DAC Output Buffer Lifetime Drift XXX
NVMCTRL Flash Multi-Page Erase Can Erase Write Protected Section XXX
NVM_EEPROM_ERASE Command does Not Respect Write Protect XXX
PORT Digital Input on Pin Automatically Disabled When Pin Selected for Analog Input XXX
RSTCTRL BOD Registers not Reset When UPDI Is Enabled XXX
TCA Restart Will Reset Counter Direction in NORMAL and FRQ Mode XXX
TCB CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode XXX
TCD Asynchronous Input Events not Working When TCD Counter Prescaler Is Used XXX
CMPAEN Controls All WOx for Alternative Pin Functions XXX
Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used XXX
TWI The Output Pin Override Does not Function as Expected XXX
Flush Non-Functional XXX
USART Open-Drain Mode Does not Work When TXD Is Configured as Output XXX
Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode XXX
Receiver Non-Functional after Detection of Inconsistent Synchronization Field XXX
ZCD All ZCD Output Selection Bits Are Tied to the ZCD0 Bit XXX
Note:
  1. This revision is the initial release of the silicon.