31.5.4 Control B
| Name: | CTRLB |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | NACKDIS | CCDETDIS | UPDIDIS | | | |
| Access | | | | R/W | R/W | R/W | | | |
| Reset | | | | 0 | 0 | 0 | | | |
Bit 4 – NACKDIS Disable NACK Response
Writing a
‘1’ to this bit disables the NACK signature sent by the UPDI
when a System Reset is issued during ongoing LD(S) and ST(S)
operations.
Bit 3 – CCDETDIS Collision and Contention Detection
Disable
Writing a
‘1’ to this bit disables the contention detection. Writing a
‘0’ to this bit enables the contention
detection.
Bit 2 – UPDIDIS UPDI
Disable
Writing a
‘1’ to this bit disables the UPDI PHY interface. The clock
request from the UPDI is lowered, and the UPDI is reset. All the UPDI PHY
configurations and keys will be reset when the UPDI is
disabled.
