31.5.8 ASI System Control A
| Name: | ASI_SYS_CTRLA |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UROWWRITE_FINAL | CLKREQ | ||||||||
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 1 – UROWWRITE_FINAL User Row Programming Done
This bit must be written when the user row data have been written to
the RAM. Writing a ‘1’ to this bit will start the process of
programming the user row data to the Flash.
If this bit is written before the user row data is written to the RAM by the UPDI, the CPU will proceed without the written data.
This bit is writable only if the USERROW-Write key is successfully decoded.
Bit 0 – CLKREQ Request System Clock
If this bit is written to ‘1’, the ASI is requesting the system
clock, independent of the system sleep modes. This makes it possible for the
UPDI to access the ACC layer, also if the system is in a sleep mode.
Writing a ‘0’ to this bit will lower the clock
request.
This bit will be reset when the UPDI is disabled.
This bit is set by default when the UPDI is enabled in any programming mode (Fuse, high-voltage).