22.5.5 Interrupt Flags
| Name: | INTFLAGS |
| Offset: | 0x06 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVF | CAPT | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – OVF Overflow Interrupt Flag
This bit is set when an overflow interrupt occurs. The flag is set whenever the timer/counter wraps from MAX to BOTTOM.
The bit is cleared by writing a ‘1’ to the bit
position.
Bit 0 – CAPT Capture Interrupt Flag
This bit is set when a capture interrupt occurs. The interrupt conditions are dependent on the Counter Mode (CNTMODE) bit field in the Control B (TCBn.CTRLB) register.
This bit is cleared by writing a ‘1’ to it or when
the Capture register is read in Capture mode.
| Counter Mode | Interrupt Set Condition | TOP Value | CAPT |
|---|---|---|---|
| Periodic Interrupt mode | Set when the counter reaches TOP | CCMP | CNT == TOP |
| Timeout Check mode | Set when the counter reaches TOP | ||
| Single-Shot mode | Set when the counter reaches TOP | ||
| Input Capture Frequency Measurement mode | Set on edge when the Capture register is loaded and the counter restarts; the flag clears when the capture is read | -- | On Event, copy CNT to CCMP, and restart counting (CNT == BOTTOM) |
| Input Capture on Event mode | Set when an event occurs and the Capture register is loaded; the flag clears when the capture is read | On Event, copy CNT to CCMP, and continue counting | |
| Input Capture Pulse-Width Measurement mode | Set on edge when the Capture register is loaded; the previous edge initialized the count; the flag clears when the capture is read | ||
| Input Capture Frequency and Pulse-Width Measurement mode | Set on the second edge (positive or negative) when the counter is stopped; the flag clears when the capture is read | ||
| 8-Bit PWM mode | Set when the counter reaches CCMH | CCML | CNT == CCMH |