14.11 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS, PCON0 and PCON1 registers are updated to indicate the cause of the Reset. The following table shows the Reset conditions of these registers.

Table 14-4. Reset Condition for Special Registers
ConditionProgram
CounterSTATUS Register(1,2)PCON0 RegisterPCON1 Register
Power-on Reset0-110 00000011 110x---- -111
Brown-out Reset0-110 00000011 11u0---- -u1u
MCLR Reset during normal operation0-uuu uuuuuuuu 0uuu---- -uuu
MCLR Reset during Sleep0-10u uuuuuuuu 0uuu---- -uuu
WDT Time-out Reset0-0uu uuuuuuu0 uuuu---- -uuu
WDT Wake-up from SleepPC + 2-00u uuuuuuuu uuuu---- -uuu
WWDT Window Violation Reset0-uuu uuuuuu0u uuuu---- -uuu
Interrupt Wake-up from SleepPC + 2(3)-10u uuuuuuuu uuuu---- -uuu
RESET Instruction Executed0-uuu uuuuuuuu u0uu---- -uuu
Stack Overflow Reset (STVREN = 1)0-uuu uuuu1uuu uuuu---- -uuu
Stack Underflow Reset (STVREN = 1)0-uuu uuuuu1uu uuuu---- -uuu
Data Protection (Fuse Fault)0-uuu uuuuuuuu uuuu---- -uu0
VREG or ULP Ready Fault0-110 00000011 110u---- -0u1
Memory Violation Reset0-uuu uuuuuuuu uuuu---- -u0u

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note:
  1. If a Status bit is not implemented, that bit will be read as ‘0’.
  2. Status bits Z, C, DC are reset by POR/BOR.
  3. When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2.