3.2.2 High-Resolution PWM with Fine Edge Placement

The trigger mechanisms are summarized in Table 3-3. PWM generators are set up to run at 100 kHz with defined dead times. The PWM generators’ setup is optimized to run purely in core independent peripherals for PSFB-CDR.

More details are available in the MCC and MPLAB projects.

Table 3-3. PWM Setup Used to Drive Primary PSFB and Secondary Current Doubler Stages
PWM Generator NumberDetailsFunctionStart of Cycle TriggerPeripheral Setting
PWM Generator 1 (PG1)

Complimentary PWM at 100 kHz at 50% duty cycle

Generating signals for the fixed leg of PSFB

Self-Triggered

PG1 end of cycle

PWM Generator 3 (PG3)

Complimentary PWM at 100 kHz at 50% duty cycle

Generating signals for the phase-shifted leg of PSFB

Phase delayed and synchronized to PG1

Trigger value from PG1

PWM Generator 2 (PG2)

Complimentary PWM at 100 kHz, swapped. Only high-side signal used

Generating the synchronous rectifier signal for SR2

Synchronized to PG3.

Duty Cycle = Period – Phase Delay

Trigger value from PG3 and swapping the high and low-side signal

PWM Generator 4 (PG4)

Complimentary PWM at 100 kHz, swapped. Only high-side signal used

Generating the synchronous rectifier signal for SR1

Synchronized to PG1. Duty Cycle = Period – Phase Delay

Trigger value from PG1 and swapping the high and low-side signal