1 Peripheral Overview
The Analog-to-Digital Converter with Computation (ADCC) is a peripheral that reads an analog voltage, transforms it into a digital value and performs various computations on the results. The ADCC input can be selected from several internal channels (Fixed Voltage Reference (FVR), temperature sensor or ground reference) or from an external pin. The ADC Positive Channel Selection (ADPCH) register selects the channel.
The ADCC can have different positive and negative references. The positive reference can be chosen by writing in the ADC Positive Voltage Reference Selection (ADPREF) bits of the ADC Reference Selection (ADREF) register. The available sources are the FVR output, the external VREF+ pin or the supply voltage (VDD). The negative reference can be selected from the ground reference (VSS) or external VREF- pin by writing in the ADC Negative Voltage Reference Selection (ADNREF) bit in the same register as before.
The ADCC has two clock sources. They are selected by the value of the Clock
Selection (ADCS) bit in the Control 0 (ADCON0) register. The value ‘0’
selects the main microcontroller clock prescaled by a value determined by the ADCLK
register. The value ‘1’ of ADCS selects the dedicated fixed-frequency
ADCC clock called FRC.
The ADCC can provide right- or left-justified results depending on the
setting of the results Format/Alignment Selection (ADFM) bit in the Control 0 (ADCON0)
register in the following way: ‘1’ for right-justified results and
‘0’ for left-justified. The result is found in the 16-bit ADC
Result (ADRES) register.
The ADCC can be configured to start conversions on a trigger signal. The trigger can come from an external pin or from other peripherals. The timing requirements for a conversion still need to be followed (e.g. if a conversion takes 100 us, then a trigger that comes faster than 100 us will not produce a new conversion).
The ADCC is enabled by setting the ADC Enable (ADON) bit in the Control 0 (ADCON0) register. There are then three ways to start a conversion. The first is by setting the ADC Conversion Status (ADGO) bit in the ADCON0 register. The second is by receiving an auto-conversion trigger that is configured for this purpose. The third is automatic, if the ADC Continuous Operation Enable (ADCONT) bit in the ADCON0 register is set. A conversion will start immediately after the end of the previous one.
The ADCC module is equipped with post-conversion computation features that can be configured through the ADC Control 2 (ADCON2) register. There are five available computation modes:
- Basic: The normal conversion mode. A single or double conversion is done and then the result is stored in the ADRES register.
- Accumulate: With each trigger, the result is right-shifted by a number of bits equal to the value in the ADC Accumulated Calculation Right Shift Select bits in the ADCON2 register and then added to the accumulator, a threshold test is performed and ADC Repeat Counter (ADCNT) register is incremented.
- Average: With each trigger, the result is right-shifted by a number of bits equal to the value in the ADCRS bits in the ADCON2 register and then added to the accumulator. When a number of conversions equal to the ADC Repeat Setting (ADRPT) is completed, the value in the accumulator is divided by the number of samples and a threshold test is performed and the accumulator is cleared on the next trigger.
- Burst average: It is similar to the Average mode, but it re-triggers the conversion until ADCNT becomes equal to ADRPT even if continuous mode is not enabled.
- Low-pass filter: It works the same as the Average mode except it performs a low-pass filtering operation on all the samples and reduces the effect of high-frequency noise on the average.
At the end of each computation, the results are latched and held stable. The error is then calculated by a formula selected by the ADC Error Calculation Mode Select (ADCALC) bits in the ADC Control 3 (ADCON3) register. The error is stored in the ADC Setpoint Error (ADERR) register.
The error is then compared to the upper and lower thresholds depending on the setting of the Threshold Interrupt Mode Select (ADTMD) bits in the ADC Control 3 (ADCON3) register and if it is between the required bounds an interrupt will be triggered.