39 Revision History

Revision A (February 2026)

This is the initial version of the document.

Revision B (September 2026)

This revision incorporates the following updates:

  • Sections:
    • Updated 3.3. Data Space Addressing, 3.5.6. Accumulator B Low Register, 4.2. Data Address Space, 5.3. Error Correcting Code (ECC), 5.4. ECC Fault Injection, 9.7. Reference Clock Output, 10.1.1. Source and Destination, 10.1.3. Trigger Source, 10.2.2. DMA Registers, 12. High-Speed PWM, 12.4. PWM4H/L Output on Peripheral Pin Select, 13.6. Wake Input (WAKE), 15. High-Speed Analog Comparator with Slope Compensation DAC, 16. Quadrature Encoder Interface (QEI), 20. Inter-Integrated Circuit (I2C), 20.2. Setting Baud Rate When Operating as a Bus Host, 20.3. Client Address Masking, 23.1. Time Base Generator, 27. Current Bias Generator (CBG), 28. Operational Amplifier, 31.2. Configuration Registers, 38.1. Package Marking Information and Product Identification System.
  • Tables:
    • Updated Table 1-2. Pinout I/O Descriptions, Table 7-1. Trap Vector Details, Table 7-2. Interrupt Vector Details, Table 20-2. I2Cx Reserved Addresses, Table 23-5. Synchronization Sources, Table 32-1. Symbols Used in Opcode Descriptions, Table 32-2. Instruction Set Overview, Table 34-5. Operating Voltage Specifications, Table 34-6. Operating Current (IDD), Table 34-7. Idle Current (IIDLE), Table 34-8. Power-Down Current (IPD), Table 34-9. Doze Current (IDOZE), Table 34-16. I/O Pin Input Injection Current Specifications, Table 34-21. PLL Clock Timing Specifications, Table 34-24. Internal LPRC Accuracy, Table 34-29. I2Cx Bus Data Timing Requirements (Host Mode), Table 34-30. I2Cx Bus Data Timing Requirements (Client Mode), Table 34-32. ADC Module Specifications, Table 34-33. Die Temperature Diode Specifications, Table 34-35. DACx Module Specifications, Table 34-36. DAC Output (DACOUT1 Pin) Specifications, Table 34-38. Operational Amplifier Specifications and Table 36-2. AC/DC Characteristics.
    • Added SPIx Module Host Mode, SPIx Module Client Mode, QEI Index Pulse Timing Requirements and Internal LPRC Accuracy.
  • Registers:
    • Updated 3.5.29. Y Page Register, 7.7.18. Interrupt Enable Register 7, 7.7.24. Interrupt Priority Register 3, 7.7.27. Interrupt Priority Register 6, 7.7.1. Interrupt Request Flags Register 0, 7.7.2. Interrupt Request Flags Register 1, 7.7.3. Interrupt Request Flags Register 2, 7.7.4. Interrupt Request Flags Register 3, 7.7.5. Interrupt Request Flags Register 4, 7.7.6. Interrupt Request Flags Register 5, 7.7.7. Interrupt Request Flags Register 6, 7.7.8. Interrupt Request Flags Register 7, 7.7.9. Interrupt Request Flags Register 10, 7.7.10. Interrupt Request Flags Register 11, 7.7.18. Interrupt Enable Register 7,7.7.24. Interrupt Priority Register 3, 7.7.27. Interrupt Priority Register 6, 7.7.40. Interrupt Priority Register 19, 7.7.43. Interrupt Priority Register 22, 7.7.49. Interrupt Priority Register 28, 7.7.60. Interrupt Control Register 3, 8.2.2.13. Analog Select for PORTB Register, 8.2.2.25. Analog Select for PORTC Register, 8.2.2.37. Analog Select for PORTD Register, 9.10.1. Oscillator Control Register, 9.10.4. PLL Output Divider Register, 10.2.3.1. DMA Engine Control Register, 10.2.3.3. DMA Low Address Limit Register, 10.2.3.4. DMA High Address Limit Register, 11.2.3. CAN Nominal Bit Time Configuration Register Low, 11.2.4. CAN Nominal Bit Time Configuration Register High, 11.2.15. CAN Interrupt Register Low, 11.2.21. CAN Receive Overflow Interrupt Status Register Low, 11.2.22. CAN Receive Overflow Interrupt Status Register High, 11.2.40. CAN Transmit Queue Control Register Low, 11.2.42. CAN Transmit Queue Status Register, 11.2.45. CAN FIFO Control Register x Low, 11.2.46. CAN FIFO Control Register x High, 11.2.47. CAN FIFO Status Register x, 11.2.48. CAN FIFO User Address Register x Low, 11.2.49. CAN FIFO User Address Register x High, 11.2.50. CAN Filter Control Register x Low, 11.2.51. CAN Filter Control Register x High, 11.2.52. CAN Filter Object Register x Low, 11.2.53. CAN Filter Object Register x High, 11.2.54. CAN Mask Register x Low, 11.2.55. CAN Mask Register x High, 12.6.12. PWM Generator x Control Register Low, 12.6.13. PWM Generator x Control Register High, 12.6.14. PWM Generator x Status Register, 12.6.15. PWM Generator x I/O Control Register Low, 12.6.17. PWM Generator x Event Register Low, 12.6.19. PWM Generator x PCI Register Low, 12.6.21. PWM Generator x PCI Register Low, 12.6.25. PWM Generator x PCI Register Low, 12.6.27. PWM Generator x Select PCI Register Low, 12.6.38. PWM Generator x Capture Register, 13.23.3. Status Register 0, 14.3.7. ADC Input Mode Control Register 0 Low, 14.3.8. ADC Input Mode Control Register 0 High, 14.3.8. ADC Input Mode Control Register 0 High, 14.3.9. ADC Input Mode Control Register 1 Low, 14.3.10. ADC Interrupt Enable Register Low, 14.3.11. ADC Interrupt Enable Register High, 14.3.12. ADC Data Ready Status Register Low, 14.3.13. ADC Data Ready Status Register High, 14.3.20. ADC Channel Trigger 0 Selection Register Low, 14.3.21. ADC Channel Trigger 0 Selection Register High, 14.3.22. ADC Channel Trigger 1 Selection Registers Low, 14.3.23. ADC Channel Trigger 1 Selection Register High, 14.3.24. ADC Channel Trigger 2 Selection Registers Low, 14.3.25. ADC Channel Trigger 2 Selection Register High, 14.3.26. ADC Channel Trigger 3 Selection Registers Low, 14.3.27. ADC Channel Trigger 3 Selection Register High, 14.3.28. ADC Channel Trigger 4 Selection Registers Low, 14.3.29. ADC Channel Trigger 4 Selection Register High, 14.3.30. ADC Channel Trigger 5 Selection Registers Low, 14.3.36. ADC Early Interrupt Status Register Low, 14.3.37. ADC Early Interrupt Status Register High, 14.3.39. ADC Control Register 5 High, 14.3.40. ADC Buffer x Register, 15.4.2. DAC Control 2 Low Register, 15.4.3. DAC Control 2 High Register, 15.4.4. DACx Control Low Register, 15.4.5. DACx Control High Register, 15.4.6. DACx Data Low Register, 15.4.7. DACx Data High Register, 15.4.8. DACx Slope Control Low Register, 15.4.9. DACx Slope Control High Register, 15.4.10. DACx Slope Data Register,16.1.4. Velocity 1 Counter Register High, 16.1.6. Position 1 Counter Hold Register, 16.1.8. Velocity 1 Counter Register, 16.1.10. Velocity 1 Counter Hold Register, 16.1.10. Velocity 1 Counter Hold Register, 16.1.16. Index 1 Counter Hold Register, 19.1.8. SPIx Baud Rate Generator Register Low, 20.5.5. I2C1 Client Mode Address Mask Register, 23.6.2. CCPx Control 1 High Register, 25.2.3. PTG Broadcast Trigger Enable Low Register, 25.2.4. PTG Broadcast Trigger Enable High Register, 25.2.14. PTG Step Queue n Pointer Register, 27.1.2. Current Bias Generator 50 μA Current Source Control Low Register, 27.1.3. Current Bias Generator 50 μA Current Source Control High Register, 28.1.2. Op Amp Control Register H, 29.1.5. Deadman Timer Count Register Low, 29.1.6. Deadman Timer Count Register High, 29.1.8. DMT Post-Configure Count Status Register Low, 29.1.9. DMT Post-Configure Count Status Register High, 29.1.10. DMT Post-Configure Interval Status Register Low, 29.1.11. DMT Post-Configure Interval Status Register High, 31.5.1. Voltage Regulator Control Register and 31.7.1. Watchdog Timer Control Register Low.
    • Added Error Trap Origination Address Register Low and Error Trap Origination Address Register High.
    • Removed Position 1 Counter Hold Register Low, Velocity 1 Counter Hold Register Low and Index 1 Counter Hold Register Low.
  • Figures
    • Updated Figure 4-6. Data Memory Map for dsPIC33CDVL256MC506 Devices, Figure 19-4. SPIx Host/Client Connection (Enhanced Buffer Modes) and Figure 31-1. POR Event on VDD.
    • Added QEI Module Index Pulse Timing Characteristics.
  • Examples:
    • Updated Example 5-1. Flash Write/Read, Example 13-1. dsPIC® DSC Auto-Baud Example and Example 30-2. PWRSAV Instruction Syntax in C Language.