6 Application Information
Layout Considerations
Layout plays a considerable role in noise and ringing in a circuit; unwanted noise coupling, unpredicted glitches and abnormal operation could arise due to poor layout of the associated components. Figure 6-1 shows a half bridge schematic with parasitic inductance in the high current path (LP1, LP2, LP3, LP4) which would be caused by inductance in the metal of the trace. Considering Figure 6-1, the length of the tracks in red should be minimized, and the bootstrap capacitor (CB) and the decoupling capacitor (CD) should be placed as close to the IC as possible. Low ESR ceramic capacitors should be used to minimize inductance. Finally, the gate resistors (RGH and RGL) and the sense resistor (RS) should be surface mount devices. These suggestions will reduce the parasitics due to the PCB traces.
Generally, for the decoupling capacitor on VCC, at least one low ESR capacitor is recommended, and it should be placed as close to the device as possible. The recommended values are 1 μF to 10 μF. A second smaller decoupling capacitor is sometimes added to provide better high frequency response (for example, 0.1 μF).
Full Bridge Converter Application Example
- RRG1, RRG2, RRG3, and RRG4 values are typically between 0Ω and 10Ω. The exact value is decided based on the MOSFET junction capacitance and the drive current of gate driver. A value of 10Ω is used in this example.
- RG1, RG2, RG3, and RG4 values are typically between 20Ω and 100Ω. The exact value is decide based on the MOSFET junction capacitance and drive current of the gate driver. A value of 50Ω is used in this example.
- RB1 and RB2 values are typically between 3Ω and 20Ω. The exact value is calculated based on the bootstrap capacitor value and the amount of current limiting required for bootstrap capacitor charging. A value of 10Ω is used in this example. Also, DB1 and DB2 should be ultra fast diodes with a minimum rating of 1A and a voltage rating greater than the system operating voltage.
- It is recommended that the input pulse (to IN and SD*) should have an amplitude of 2.5V minimum (for VDD = 15V), with a minimum pulse width of 800 ns.