1.9.1 Synchronous Mode Transmissions

In synchronous mode if the TXREG is loaded with a new byte while the EUSART is shifting out the 8th bit of the previous byte, then only one bit of the new byte gets shifted out. After this bit is shifted out, the transmission stops and the data is lost. If using 9-bit transmission, then this occurs on the 9th bit.

Work around

Write to the TXREG earlier in the transmission or wait for the TXIF flag bit to be set before writing a second byte.

Affected Silicon Revisions