30.6.3.10 Sample Adjustment

In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A register (CTRLA.SAMPA). When CTRLA.SAMPA=0, samples 7-8-9 are used for 16x oversampling, and samples 3-4-5 are used for 8x oversampling.

Note: In full asynchronous mode, the start-of-frame event may not occur with a rising edge of the UART clock reference. As a result, the counter may transition from 0 to 1 in less than one UART clock reference period. After initialization, the counter increments on every subsequent rising edge of the UART clock reference, independent of the incoming data bits.