23.1 Fundamental Operation
The PWM module produces a 10-bit resolution output. The timer selection for PWMx is TMR2. T2TMR and T2PR set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled.
Important: The Timer2
postscaler is not used in the determination of the PWM frequency. The postscaler might be
used to have a servo update rate at a different frequency than the PWM output.
All PWM outputs associated with Timer2 are set when T2TMR is cleared. Each PWMx is cleared when T2TMR is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL[7:6] (2 LSb) registers. When the value is greater than or equal to T2PR, the PWM output is never cleared (100% duty cycle).
Important: The PWMxDCH and PWMxDCL registers are
double-buffered. The buffers are updated when T2TMR matches
T2PR. Care has to be taken to update both registers
before the timer match occurs.