23.4 PWM Duty Cycle

The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the two LSbs, PWMxDCL[7:6]. The PWMxDCH and PWMxDCL registers can be written to at any time.

The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio.

Equation 23-2. Pulse Width
P u l s e ⁢   W i d t h = ( P W M x D C H : P W M x D C L [ 7 : 6 ] ) • T o s c • ( T M R 2 ⁢   Pr e s c a l e ⁢   ⁢ V a l u e )
Note: TOSC = 1/FOSC
Equation 23-3. Duty Cycle Ratio
D u t y C y c l e R a t i o = ( P W M x D C H : P W M x D C L [ 7 : 6 ] ) 4 ( T 2 P R + 1 )

The 8-bit timer T2TMR register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.