24.3.3.1.8 8-Bit PWM Mode

The TCB peripheral can be configured to run in 8-bit PWM mode, where each register pair in the 16-bit Capture/Compare (TCBn.CCMPH and TCBn.CCMPL) registers are used as individual Compare registers. CCMPL controls the period (T), while CCMPH controls the waveform duty cycle. The counter will continuously count from BOTTOM to CCMPL, and the output will be set at BOTTOM and cleared when the counter reaches CCMPH.

CCMPH is the number of cycles for which the output will be driven high. CCMPL+1 is the output pulse period, the +1 resulting in an observed delay of one clock cycle.