5.2 User Interface
I/O Pins
The PIC16F, PIC18F and PIC32CM MCUs provide highly configurable I/O pin controllers that allow individual pin configurations, including interrupt or event generation on pin changes, and peripheral multiplexing for flexible hardware designs. The table below provides a comparison of the features of the PIC16F, PIC18F, and PIC32CM MCUs.
| Feature | PIC16F | PIC18F | PIC32CM |
|---|---|---|---|
| Port Group Size | Up to 8 pins per PORT | Up to 8 pins per PORT | Up to 32 pins per PORT |
| Pin Multiplexing | Peripheral Pin Select (PPS) or
Alternate Pin Function Control (APFCON) for digital signal
remapping Analog functions are generally fixed to specific pins | Peripheral Pin Select (PPS) for
digital signal remapping Analog functions are generally fixed to specific pins | Software-controlled, highly flexible with Peripheral Multiplexing (PMUX) |
| Read-Modify-Write (RMW) | Handled through Data Latch (LATx) | Handled through Data Latch (LATx) | Atomic RMW through 8-bit/16-bit/32-bit writes |
| Input Sensing/Interrupts | Configurable input
sampling Interrupt-on-Change (IOC) | Configurable input sampling IOC | Configurable input sampling IOC |
| Pull Configuration | Internal weak pull-up (WPU) | Internal WPU | Pull-up Pull-down Driver strength Buffer control |
| Voltage Domains | No native MVIO All pins share the same supply | Single VDD Multi-Voltage I/O (MVIO) support for some device families | No native MVIO All pins share the same supply |
| Supply Status Monitoring | MVIO-only | MVIO-only | Not available |
| Peripheral Override | Supported | Supported | Supported |
| I/O Bus Access | Single-cycle access available for SFRs via the Access Bank | Single-cycle access available for SFRs via the Access Bank | AHB/APB bridge Arm® single-cycle IOBUS |
| Output Driver Options | – | Slew Rate Control Open-Drain Control | Push-pull Open-drain Tri-state Configurable driver strength Slew Rate Limiting |
| Input Buffer Control | Supported | Supported | Supported |
| Pin Configuration | TRIS registers (input/output) | TRIS registers (input/output) | PORT registers, advanced configuration |
| Event System | N/A | N/A | Integrated with the pin controller |
| Debounce/Filtering | N/A | N/A | Available on some pins |