5.1.6 Device Memory Access (DMA) Controller
The PIC18F and PIC32CM Direct Memory Access (DMA) controllers enable high-speed data transfers between memory and peripheral registers without CPU intervention. This improves system efficiency, reduces CPU load, and enables real-time data handling for tasks, such as serial communication, ADC sampling, and port memory-to-memory transfers. The table below provides a comparison of the features of the PIC18F and PIC32CM MCUs.
| Feature/Aspect | PIC18F DMA | PIC32CM DMAC |
|---|---|---|
| DMA Channels | Up to 8 | Up to 16 |
| Transfer Types | Peripheral-to-memory, memory-to-peripheral | Peripheral-to-memory, memory-to-peripheral, memory-to-memory |
| Trigger Sources |
Software triggers Hardware triggers |
Peripheral events Software triggers External triggers |
| Addressing Modes | Fixed, increment, or decrement | Fixed, increment, or decrement |
| Burst/Block Transfer | Byte-at-a-time | Supported |
| Priority Levels | Managed through System Arbiter | Programmable priorities |
| Descriptor Support | None, uses dedicated registers for each transfer |
Advanced (linked list descriptors for complex transfers) |
| Data Width | 8-bit | 8-bit/16-bit/32-bit |
| Interrupt Support | Supported | Supported |
| CRC Check | Through separate CRC | Built-in |
| Configuration | Basic, through SFRs | Advanced, through registers and descriptors |
| CPU Offload | Supported | Supported |
| Power Efficiency | Improved | High (DMA operates in Sleep mode/Standby mode) |