5.1.3 Power Management
The PIC16F, PIC18F and PIC32CM MCUs provide advanced low-power management features to minimize energy consumption during periods of inactivity. These MCUs offer multiple low-power modes, such as Idle and Standby, allow the CPU to halt execution while retaining SRAM and register contents, and support wake up from sleep through interrupts or reset events. The application determines which sleep mode to enter, and peripherals can be selectively enabled or disabled in certain low-power modes. These features make all three MCUs suitable for battery-powered and energy-sensitive applications. Table 5-5 provides a comparison of features between PIC16F, PIC18F and PIC32CM.
| Feature | PIC16F Power Saving Modes | PIC18F Power Saving Modes | PIC32CM Power Manager (PM) |
|---|---|---|---|
| Integration | Managed through core registers and Configuration bits | Managed through core registers and Configuration bits | Integrated into the Power Manager (PM) peripheral |
| Low-Power or Sleep modes |
Sleep Idle Doze |
Sleep Idle Doze Deep Sleep Peripheral Module Disable (PMD) |
Idle Standby Hibernate Backup Off |
| Power Consumption (Sleep) | Low (µA range) |
Low (µA range) Ultra-low (nA in Deep Sleep) |
Low (µA range) Ultra-low (nA in Standby/Off) |
| SleepWalking | Supported through asynchronous Core-Independent Peripherals (CIPs) and Analog Peripheral Manager (APM) | Supported through asynchronous CIPs and APM | Supported (in Standby, Hibernate, on GCLK clocks) |
| Power Domain Gating | Static (through Peripheral Module Disable (PMD)) or Dynamic (through APM) | Static (through PMD) or Dynamic (through APM) | Static (ON/OFF) or Dynamic in Standby/Hibernate |
| I/O State Retention | Supported | Supported | Supported |
| SRAM/Registers Retention | Supported | Supported | Supported |
| Wake-up Sources |
Interrupts Resets |
Interrupts Resets |
Interrupts Resets |