5.1.1 Clock Selection

The PIC16F, PIC18F and PIC32CM MCUs offer flexible and robust clock systems that support multiple internal and external clock sources, programmable prescalers and safe run-time switching. The PIC16F, PIC18F and PIC32CM MCUs allow peripherals to request and receive clocks as needed, support low-frequency and high-frequency oscillators, and provide mechanisms for clock accuracy tuning and failure detection. The main clock can be prescaled, and peripherals can operate either synchronously or asynchronously with respect to the main clock. These features enable efficient power management, high performance and reliable operation across a wide range of applications.

The main difference between PIC16F, PIC18F and PIC32CM is in the way clock management is integrated within the MCU. The PIC16F and PIC18F MCUs use the device configuration bits and an Oscillator Module (OSC), while the PIC32CM MCUs (depending on the family of devices) implement a Clock System that uses a combination of the Generic Clock Controller (GCLK), Main Clock Controller (MCLK), System Controller (SYSCTRL), Oscillator Controllers (OSCCTRL, OSC32KCTRL) and Power Manager (PM). Table 5-3 provides a comparison of features between PIC16F, PIC18F and PIC32CM.

Table 5-3. PIC16F, PIC18F and PIC32CM Clock Selection Features
FeaturePIC16F Oscillator Module (OSC)PIC18F Oscillator Module (OSC)PIC32CM Clock System

(GCLK, MCLK, SYSCTRL, OSCCTRLs, PM)

Main Clock Source

Selectable internal/external

FOSC up to 32 MHz

Selectable internal/external

FOSC up to 64 MHz

Selectable through GCLK

Up to 48 MHz OSC48M, 96 MHz FDPLL

Internal Oscillators

HFINTOSC (up to 16 MHz)

MFINTOSC (500 kHz)

LFINTOSC (31 kHz)

ADCRC (dedicated for ADC)

HFINTOSC (up to 64 MHz)

MFINTOSC (500 kHz)

LFINTOSC (31 kHz)

ADCRC (dedicated for ADC)

OSC8M

OSC48M

OSC32K

OSCULP32K

OSCHF (up to 24 MHz)

External Oscillators

LP, XT, HS

EC, RC/EXTRC,

SOSC

LP, XT, HS, HSPLL

EC, RC, SOSC

0.4–32 MHz XOSC, 32.768 kHz XOSC32K External clock
PLL/DFLL/DPLL4x PLL4x PLL

DFLL48M (48 MHz)

FDPLL96M (48–96 MHz)

Clock Distribution

FOSC

CLKOUT

CLKREF

FOSC

CLKOUT

CLKREF

GCLK and peripheral channels
Prescaler Range1x to 512x1x to 256x1x to 128x (GCLK, MCLK)
Clock Domains

Primary OSC

Secondary OSC

Internal OSC Block

Primary OSC

Secondary OSC

Internal OSC Block

Core

AHB, multiple APBx( 1)

Per-peripheral domains

Safe Run-Time SwitchingSupported (IESO/TSSU)Supported (CSWEN, IESO)Supported (GCLK, MCLK)
Clock Gating/MaskingSupported in low-power modes (Sleep, Idle, PMD)Supported in low-power modes (Sleep, Idle, PMD)Module-level clock gating through masks
Clock Failure DetectionFail-Safe Clock Monitor (FSCM)Fail-Safe Clock Monitor (FSCM)Automatic detection
Calibration/Auto-TuningFactory-calibrated

Manual tuning

Factory-calibrated

Manual/auto-tuning

Factory calibration fine tuning
Power Management IntegrationIntegrated in low-power modesIntegrated in low-power modesPower domain gating wake-up on clock events
Brown-out DetectorSupported (BOR)Supported (BOR)BOD33 integrated can trigger wake-up
Note:
  1. Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) are two types of internal bus architectures used in Arm-based microcontrollers. These buses are used to connect the CPU, memory and peripherals.