2.3 LVPECL Application

The VC-709 incorporates a standard PECL output scheme, which are unterminated FET drains. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 2-6, or for best 50Ω matching a pull-up/pull-down scheme as shown in Figure 2-7 should be used. AC coupling capacitors are optional, depending on the application and the input logic requirements of the next stage.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left unterminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50Ω impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems.

As shown in the figure below, resistor values are typically 140Ω for 3.3V operation and 84Ω for 2.5V operation.

Figure 2-6. LVPECL Single Resistor Termination Scheme

As shown in the figure below, resistor values shown are typical for 3.3V operation. For 2.5V operation, the resistor to ground is 62Ω and the resistor to supply is 250Ω.

Figure 2-7. LVPECL Pull-Up Pull Down Termination