4 Port Description

Table 4-1. Fabric CCC Port Description
Port Name	Direction	Polarity	Description
CCC_[0/1]_CLK0_PAD	Input	—	Input clock when using Dedicated Input Pad 0 configured as a single-ended I/O.
CCC_[0/1]_CLK0_[PADP and PADN]	Input	—	Input clock when using Dedicated Input Pad 0 configured as differential I/O. P side and N side.
CCC_[0/1]_CLK1_PAD	Input	—	Input clock when using Dedicated Input Pad 1 configured as a single-ended I/O.
CCC_[0/1]_CLK1_[PADP and PADN]	Input	—	Input clock when using Dedicated Input Pad 1 configured as differential I/O. P side and N side.
CCC_[0/1]_CLK2_PAD	Input	—	Input clock when using Dedicated Input Pad 2 configured as a single-ended I/O.
CCC_[0/1]_CLK2_[PADP and PADN]	Input	—	Input clock when using Dedicated Input Pad 2 configured as differential I/O. P side and N side.
CCC_[0/1]_CLK3_PAD	Input	—	Input clock when using Dedicated Input Pad 3 configured as a single-ended I/O.
CCC_[0/1]_CLK3_[PADP and PADN]	Input	—	Input clock when using Dedicated Input Pad 3 configured as differential I/O. P side and N side.
CCC_[0/1]_CLK0_SPWR_STROBE_[PADP and PADN]	Input	—	Input Clock when Dedicated pad 0 is used as input to Strobe of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.
CCC_[0/1]_CLK1_SPWR_DATA_[PADP and PADN]	Input	—	Input Clock when Dedicated Pad 1 is used as input to Data of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.
CCC_[0/1]_CLK2_SPWR_STROBE_[PADP and PADN]	Input	—	Input Clock when Dedicated pad 2 is used as input to Strobe of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.
CCC_[0/1]_CLK3_SPWR_DATA_[PADP and PADN]	Input	—	Input Clock when Dedicated Pad 3 is used as input to Data of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.
CCC_[0/1]_CLK0_SPWR_STROBE_PAD	Input	—	Input Clock when Dedicated pad 0 is used as input to Strobe of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.
CCC_[0/1]_CLK1_SPWR_DATA_PAD	Input	—	Input Clock when Dedicated pad 1 is used as input to Data of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.
CCC_[0/1]_CLK2_SPWR_STROBE_PAD	Input	—	Input Clock when Dedicated pad 2 is used as input to Strobe of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.
CCC_[0/1]_CLK3_SPWR_DATA_PAD	Input	—	Input Clock when Dedicated pad 3 is used as input to Data of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.
CCC_[0/1]_CLK0	Input	—	Input clock from FPGA core when using FPGA Fabric Input 0.
CCC_[0/1]_CLK1	Input	—	Input clock from FPGA core when using FPGA Fabric Input 1.
CCC_[0/1]_CLK2	Input	—	Input clock from FPGA core when using FPGA Fabric Input 2.
CCC_[0/1]_CLK3	Input	—	Input clock from FPGA core when using FPGA Fabric Input 3.
CCC_[0/1]_RCOSC_50MHZ	Input	—	Input clock when using 50 MHz Oscillator.
CCC_[0/1]_GL0	Output	—	Generated clock driving FPGA fabric global network 0.
CCC_[0/1]_GL1	Output	—	Generated clock driving FPGA fabric global network 1.
CCC_[0/1]_GL2	Output	—	Generated clock driving FPGA fabric global network 2.
CCC_[0/1]_GL3	Output	—	Generated clock driving FPGA fabric global network 3.
CCC_[0/1]_GL0_Y0_EN	Input	High	Enable signal for the clock driving FPGA fabric global network 0 (GL0) and fabric local routing (Y0) network 0.
CCC_[0/1]_GL1_Y1_EN	Input	High	Enable signal for the clock driving FPGA fabric global network1 (GL1) and fabric local routing (Y1) network 1.
CCC_[0/1]_GL2_Y2_EN	Input	High	Enable signal for the clock driving FPGA fabric global network 2 (GL2) and fabric local routing (Y2) network 2.
CCC_[0/1]_GL3_Y3_EN	Input	High	Enable signal for the clock driving FPGA fabric global network 3 (GL3) and fabric local routing (Y3) network 3.
CCC_[0/1]_GL0_Y0_ARST_N	Input	Low	(GL0/Y0) CGL reset signal. Asynchronous reset signal.
CCC_[0/1]_GL1_Y1_ARST_N	Input	Low	(GL1/Y1) CGL reset signal. Asynchronous reset signal.
CCC_[0/1]_GL2_Y2_ARST_N	Input	Low	(GL2/Y2) CGL reset signal. Asynchronous reset signal.
CCC_[0/1]_GL3_Y3_ARST_N	Input	Low	(GL3/Y3) CGL reset signal. Asynchronous reset signal.
CCC_[0/1]_Y0	Output	—	Generated clock driving FPGA fabric local routing resource.
CCC_[0/1]_Y1	Output	—	Generated clock driving FPGA fabric local routing resource.
CCC_[0/1]_Y2	Output	—	Generated clock driving FPGA fabric local routing resource.
CCC_[0/1]_Y3	Output	—	Generated clock driving FPGA fabric local routing resource.
CCC_[0/1]_RX0_DATA_PORT	Output	—	Output port for RX0 data. Same signal that is driving the RX0 Spacewire clock recovery data input.
CCC_[0/1]_RX1_DATA_PORT	Output	—	Output port for RX1 data. Same signal that is driving the RX1 Spacewire clock recovery data input.
CCC_[0/1]_LOCK	Output	High	PLL Lock indicator signal. This signal is asserted (lock) high.
CCC_[0/1]_PLL_BYPASS_N	Input	Low	Powers-down the PLL core and bypasses it such that PLL_OUT tracks reference clock. This has higher priority than reset.
CCC_[0/1]_PLL_POWERDOWN_N	Input	Low	Powers-down the PLL for the lowest quiescent current and the PLL outputs are low. This has higher priority than reset and bypass.
PLL_RST_N	Input	Low	PLL_RST_N is internally synchronized with CLK_50MHZ. Synchronization method can be selected using Reset type option. If Reset type selected is Synchronous then assertion and de-assertion of reset is synchronous to CLK_50MHZ. For successful synchronization, PLL_RST_N must be asserted for a minimum of three clock cycles of CLK_50MHZ. If Reset type selected is Async-Assert, Sync-Deassert then assertion of reset is asynchronous and de-assertion is synchronous with CLK_50MHZ.
READY_VDDPLL	Input	High	Tie to High if you are certain that VDDPLL not the last supply to ramp up. Otherwise, connect to a circuit that delays the assertion of VDDPLL by 73 ms as described in the UG0586: RTG4 FPGA Clocking Resources User Guide .
CLK50_MHZ	Input	—	Input clock for soft logic that performs calibration at power-up or when the PLL is reset. The frequency of this clock must be 50 MHz max. You may connect to the GLx output of any CCC that is distributing the RCOSC_50MHZ signal. You cannot directly connect a RCOSC_50MHZ macro to this input port. Alternatively, an external free-running oscillator clock can be used as long as the frequency is 50 MHz or less. CLK_50MHZ will be used for the APB3 interface when "Enable Dynamic configuration" is selected in the configurator.
Fabric CCC Configuration bus Interface Signals – APB3 bus Interface
APB_S_PRESET_N	Input	Low	APB3 interface is a active-low reset signal. You have to synchronize APB_S_PRESET_N with CLK_50MHZ externally.
APB_S_PADDR[8:2]	Input	—	APB3 interface is an address bus. This port is used to address fabric CCC internal registers. APB_S_PADDR shall be synchronous with CLK_50MHZ.
APB_S_PSEL	Input	—	APB3 interface target is a select signal. APB_S_PSEL shall be synchronous with CLK_50MHZ.
APB_S_PENABLE	Input	High	APB3 interface is a strobe signal to indicate the second cycle of an APB3 transfer. APB_S_PENABLE shall be synchronous with CLK_50MHZ.
APB_S_PWRITE	Input	—	APB3 interface is a read/write-control signal. When high, this signal indicates an APB3 write access and when low, a read access. APB_S_PWRITE shall be synchronous with CLK_50MHZ.
APB_S_PWDATA[7:0]	Input	—	APB3 interface is a write data bus. APB_S_PWDATA shall be synchronous with CLK_50MHZ.
APB_S_PRDATA[7:0]	Output	—	APB3 interface is a read data bus. APB_S_PRDATA is synchronous with CLK_50MHZ.
APB_S_PREADY	Output	—	APB3 interface is a ready indication output to initiator. APB_S_PREADY is synchronous with CLK_50MHZ.
APB_S_PSLVERR	Output	—	APB3 interface error indication signal. APB_S_PSLVERR is synchronous with CLK_50MHZ.

CCC_[0/1]_CLK0_PAD

Input

—

Input clock when using Dedicated Input Pad 0 configured as a single-ended I/O.

CCC_[0/1]_CLK0_[PADP and PADN]

Input

—

Input clock when using Dedicated Input Pad 0 configured as differential I/O. P side and N side.

CCC_[0/1]_CLK1_PAD

Input

—

Input clock when using Dedicated Input Pad 1 configured as a single-ended I/O.

CCC_[0/1]_CLK1_[PADP and PADN]

Input

—

Input clock when using Dedicated Input Pad 1 configured as differential I/O. P side and N side.

CCC_[0/1]_CLK2_PAD

Input

—

Input clock when using Dedicated Input Pad 2 configured as a single-ended I/O.

CCC_[0/1]_CLK2_[PADP and PADN]

Input

—

Input clock when using Dedicated Input Pad 2 configured as differential I/O. P side and N side.

CCC_[0/1]_CLK3_PAD

Input

—

Input clock when using Dedicated Input Pad 3 configured as a single-ended I/O.

CCC_[0/1]_CLK3_[PADP and PADN]

Input

—

Input clock when using Dedicated Input Pad 3 configured as differential I/O. P side and N side.

CCC_[0/1]_CLK0_SPWR_STROBE_[PADP and PADN]

Input

—

Input Clock when Dedicated pad 0 is used as input to Strobe of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.

CCC_[0/1]_CLK1_SPWR_DATA_[PADP and PADN]

Input

—

Input Clock when Dedicated Pad 1 is used as input to Data of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.

CCC_[0/1]_CLK2_SPWR_STROBE_[PADP and PADN]

Input

—

Input Clock when Dedicated pad 2 is used as input to Strobe of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.

CCC_[0/1]_CLK3_SPWR_DATA_[PADP and PADN]

Input

—

Input Clock when Dedicated Pad 3 is used as input to Data of Clock Recovery Circuitry in differential-mode. SpaceWire Mode only.

CCC_[0/1]_CLK0_SPWR_STROBE_PAD

Input

—

Input Clock when Dedicated pad 0 is used as input to Strobe of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.

CCC_[0/1]_CLK1_SPWR_DATA_PAD

Input

—

Input Clock when Dedicated pad 1 is used as input to Data of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.

CCC_[0/1]_CLK2_SPWR_STROBE_PAD

Input

—

Input Clock when Dedicated pad 2 is used as input to Strobe of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.

CCC_[0/1]_CLK3_SPWR_DATA_PAD

Input

—

Input Clock when Dedicated pad 3 is used as input to Data of Clock Recovery Circuitry configured as single-ended I/O. SpaceWire Mode only.

CCC_[0/1]_CLK0

Input

—

Input clock from FPGA core when using FPGA Fabric Input 0.

CCC_[0/1]_CLK1

Input

—

Input clock from FPGA core when using FPGA Fabric Input 1.

CCC_[0/1]_CLK2

Input

—

Input clock from FPGA core when using FPGA Fabric Input 2.

CCC_[0/1]_CLK3

Input

—

Input clock from FPGA core when using FPGA Fabric Input 3.

CCC_[0/1]_RCOSC_50MHZ

Input

—

Input clock when using 50 MHz Oscillator.

CCC_[0/1]_GL0

Output

—

Generated clock driving FPGA fabric global network 0.

CCC_[0/1]_GL1

Output

—

Generated clock driving FPGA fabric global network 1.

CCC_[0/1]_GL2

Output

—

Generated clock driving FPGA fabric global network 2.

CCC_[0/1]_GL3

Output

—

Generated clock driving FPGA fabric global network 3.

CCC_[0/1]_GL0_Y0_EN

Input

High

Enable signal for the clock driving FPGA fabric global network 0 (GL0) and fabric local routing (Y0) network 0.

CCC_[0/1]_GL1_Y1_EN

Input

High

Enable signal for the clock driving FPGA fabric global network1 (GL1) and fabric local routing (Y1)

network 1.

CCC_[0/1]_GL2_Y2_EN

Input

High

Enable signal for the clock driving FPGA fabric global network 2 (GL2) and fabric local routing (Y2) network 2.

CCC_[0/1]_GL3_Y3_EN

Input

High

Enable signal for the clock driving FPGA fabric global network 3 (GL3) and fabric local routing (Y3) network 3.

CCC_[0/1]_GL0_Y0_ARST_N

Input

Low

(GL0/Y0) CGL reset signal. Asynchronous reset signal.

CCC_[0/1]_GL1_Y1_ARST_N

Input

Low

(GL1/Y1) CGL reset signal. Asynchronous reset signal.

CCC_[0/1]_GL2_Y2_ARST_N

Input

Low

(GL2/Y2) CGL reset signal. Asynchronous reset signal.

CCC_[0/1]_GL3_Y3_ARST_N

Input

Low

(GL3/Y3) CGL reset signal. Asynchronous reset signal.

CCC_[0/1]_Y0

Output

—

Generated clock driving FPGA fabric local routing resource.

CCC_[0/1]_Y1

Output

—

Generated clock driving FPGA fabric local routing resource.

CCC_[0/1]_Y2

Output

—

Generated clock driving FPGA fabric local routing resource.

CCC_[0/1]_Y3

Output

—

Generated clock driving FPGA fabric local routing resource.

CCC_[0/1]_RX0_DATA_PORT

Output

—

Output port for RX0 data. Same signal that is driving the RX0 Spacewire clock recovery data input.

CCC_[0/1]_RX1_DATA_PORT

Output

—

Output port for RX1 data. Same signal that is driving the RX1 Spacewire clock recovery data input.

CCC_[0/1]_LOCK

Output

High

PLL Lock indicator signal. This signal is asserted (lock) high.

CCC_[0/1]_PLL_BYPASS_N

Input

Low

Powers-down the PLL core and bypasses it such that PLL_OUT tracks reference clock. This has higher priority than reset.

CCC_[0/1]_PLL_POWERDOWN_N

Input

Low

Powers-down the PLL for the lowest quiescent current and the PLL outputs are low. This has higher priority than reset and bypass.

PLL_RST_N

Input

Low

PLL_RST_N is internally synchronized with CLK_50MHZ. Synchronization method can be selected using Reset type option. If Reset type selected is Synchronous then assertion and de-assertion of reset is synchronous to CLK_50MHZ. For successful synchronization, PLL_RST_N must be asserted for a minimum of three clock cycles of CLK_50MHZ. If Reset type selected is Async-Assert, Sync-Deassert then assertion of reset is asynchronous and de-assertion is synchronous with CLK_50MHZ.

READY_VDDPLL

Input

High

Tie to High if you are certain that VDDPLL not the last supply to ramp up. Otherwise, connect to a circuit that delays the assertion of VDDPLL by 73 ms as described in the UG0586: RTG4 FPGA Clocking Resources User Guide .

CLK50_MHZ

Input

—

Input clock for soft logic that performs calibration at power-up or when the PLL is reset. The frequency of this clock must be 50 MHz max. You may connect to the GLx output of any CCC that is distributing the RCOSC_50MHZ signal. You cannot directly connect a RCOSC_50MHZ macro to this input port. Alternatively, an external free-running oscillator clock can be used as long as the frequency is 50 MHz or less.

CLK_50MHZ will be used for the APB3 interface when "Enable Dynamic configuration" is selected in the configurator.

Fabric CCC Configuration bus Interface Signals – APB3 bus Interface

APB_S_PRESET_N

Input

Low

APB3 interface is a active-low reset signal. You have to synchronize APB_S_PRESET_N with CLK_50MHZ externally.

APB_S_PADDR[8:2]

Input

—

APB3 interface is an address bus. This port is used to address fabric CCC internal registers. APB_S_PADDR shall be synchronous with CLK_50MHZ.

APB_S_PSEL

Input

—

APB3 interface target is a select signal. APB_S_PSEL shall be synchronous with CLK_50MHZ.

APB_S_PENABLE

Input

High

APB3 interface is a strobe signal to indicate the second cycle of an APB3 transfer. APB_S_PENABLE shall be synchronous with CLK_50MHZ.

APB_S_PWRITE

Input

—

APB3 interface is a read/write-control signal. When high, this signal indicates an APB3 write access and when low, a read access. APB_S_PWRITE shall be synchronous with CLK_50MHZ.

APB_S_PWDATA[7:0]

Input

—

APB3 interface is a write data bus. APB_S_PWDATA shall be synchronous with CLK_50MHZ.

APB_S_PRDATA[7:0]

Output

—

APB3 interface is a read data bus. APB_S_PRDATA is synchronous with CLK_50MHZ.

APB_S_PREADY

Output

—

APB3 interface is a ready indication output to initiator. APB_S_PREADY is synchronous with CLK_50MHZ.