5 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.


Revision	Date	Description
E	08/2022	The following is a summary of changes in revision E of the document: Updated Output Resynchronization After Lock Configuration Updated Miscellaneous Options
D	12/2021	The following is a summary of changes in revision D of the document: Updated Output Clocks Selection Removed "Output Clock Frequency" section Updated Miscellaneous Options
C	08/2021	The following is a summary of changes in revision C of the document: Updated Constraints Added Note in Held output in reset (output low) after power-up. Released and resynchronized with the PLL reference clock after the PLL locked
B	08/2021	The following is a summary of changes in revision B of the document: Added Calibration Added Reset Type Added Constraints Added Note regarding APB_S_PCLK Updated Introduction Updated Table 4-1
A	04/2021	The following is a summary of changes in revision A of the document: Gated Clock Configuration- Added information about slow GL or Y's Miscellaneous Options-Added message that appears during simualtions Lock Control- Added note that users should not leave the LOCK output ports CCC_0_LOCK and CCC_1_LOCK dangling because it will cause synthesis optimization that will lead to Derive Constraints failure during Place and Route

Libero® SoC v2022.2

5 Revision History