Introduction

The RTG4™ FCCC with Enhanced PLL Calibration Configurator generated circuit includes soft logic that performs calibration at power-up or when the PLL is reset. This ensures that the PLL lock is stable during normal operation within the supported RTG4 operating junction temperature range.

This document describes the RTG4 FCCC with Enhanced PLL Calibration Configurator. This configurator enables the configuration of two CCCs —CCC_0 and CCC_1. You must configure one or both of the CCCs. Enhanced lock PLL calibration soft logic is implemented for all the configured CCCs.

The enhanced PLL calibration removes any Fabric PLL lock stability dependence on the operating junction temperature across the supported RTG4 operating temperature range for non-triplicated PLL. For more information about the configuration options for the RTG4 FCCC with Enhanced PLL Calibration Configurator, see Configuration Options.

The following figure shows the top-view of the RTG4 FCCC with Enhanced PLL Calibration Configurator.

Figure . RTG4 FCCC with Enhanced PLL Calibration Configurator

The RTG4 FCCC with Enhanced PLL Calibration Configurator enables you to configure two of the eight CCC/PLL blocks available on the RTG4 devices.

Figure . Clock Paths Overview

The Fabric CCC can condition up to 11 input clocks to generate up to four clocks. Each of the four output clocks can directly drive the global network and/or the local routing network.

Each of the four output clocks can be driven by:

  • One of the eight PLL output phases
  • One of the four General Purpose Divider (GPD) outputs
  • One of the eleven input clocks:
    • Dedicated Input Pad 0
    • Dedicated Input Pad 1
    • Dedicated Input Pad 2
    • Dedicated Input Pad 3
    • FPGA Fabric Input 0
    • FPGA Fabric Input 1
    • FPGA Fabric Input 2
    • FPGA Fabric Input 3
    • 50 MHz On-chip Oscillator
    • Clock Recovery Circuitry 0
    • Clock Recovery Circuitry 1

The reference clock of the PLL can be driven by one of the nine input clocks:

  • Four Dedicated Input Pads
  • Four FPGA Fabric Inputs
  • 50 MHz On-chip Oscillator

Each of the four GPDs can be driven by either one of the nine input clocks (Dedicated Input Pad 0 through 3, Dedicated Fabric Input 0 through 3, and the 50 MHz Oscillator) or one of the eight PLL output phases. The configuration of the CCC can be broken down into the following three major blocks:

  • Output Clocks GL[x]/Y[x] configuration
    • Clock source selection
    • Clocks frequency and phase configurations
  • PLL configuration
    • PLL clock generation configuration including external feedback support
  • GPD configuration