2.3 Further Discussions

So far we have shown how the two solutions work. Experiments show both works for the typical three scenarios as shown in Figure 2-2. Both provide a very fast reaction with the debounce time at 3 ms as demonstrated, while existing solutions may require up to 20-200 ms debounce time. In contrast, no existing solutions cover all the three scenarios with no unexpected debouncing occurring.

When a series of noisy pulses occur consecutively as shown in Figure 2-2.c, there is still a probability that debouncing occurs if noisy pulses get caught at the two consecutive rising CLC clock edges. The user needs to define whether it should be considered as a stable input pulse with valid debouncing output generated or not. If it is not considered as valid debouncing, the suggestion on how to reduce the possibility is to use more stages of CLCs and/or to extend the CLC clock period. For example, introducing another stage of CLC means further check of noise pulse occurrence on the input signal at the third consecutive clock cycle and hence reduce the possibility for unexpected debouncing to be recognized. For 2-CLCs solution, another stage of CLC means 3-CLCs are required. For the 3-CLCs solution, it means four CLCs are required. On the other hand, it also helps when the CLC clock period gets prolonged. When the CLC clock period gets prolonged, more noise pulses will get filtered out during one clock period and fewer noise pulses would occur at the next CLC clock cycle.

This document describes debouncing of up to four buttons with the 2-CLCs solution on the PIC18F Q10 family devices with eight CLCs available. Or it can support debouncing of three buttons by choosing two 3-CLCs solutions and one 2-CLCs solution. It can also be adapted to support fewer buttons with more CLCs per button if preferred, depending on the user’s requirement.

So far we have discussed how to use a timer to provide a configurable clock frequency to CLCs. An alternative is to use the main clock at a lower frequency as the CLC clock frequency if it satisfies the user’s requirement. The timer will be saved if the main clock is slow enough for the CLC and this save can further reduce power consumption.