1.13 s13: Increased packet latency and coordinator anomalies in large PLCA segments

Description

The PLCA sublayer includes a FIFO which acts as an elastic buffer to align transmit packets coming from the MAC with the device’s transmit opportunity. If a MAC begins data transmission outside of a valid transmit opportunity, the elastic buffer will store MAC transmit data until it is full. If the transmit opportunity starts before this buffer is full, data will be transmitted onto the mixing segment delayed by the FIFO. If the elastic buffer fills before the transmit opportunity starts, a logical collision is signaled to the MAC and carrier sense is held asserted. The MAC will stop transmitting the packet, back off, and retransmit the packet at the device’s next appropriate transmit opportunity. The device indicates this transmit opportunity by de-asserting carrier sense.

In the event that the PLCA elastic buffer becomes full at the same time as the assigned transmit opportunity begins, the device will exhibit the following deviations from expected behavior:

  1. The device will assert carrier sense for only a short time.
  2. The device will transmit a single ‘J’ symbol on TRXN/P during the node’s transmit opportunity instead of a valid Ethernet packet.
Additionally, in a coordinator, when the PLCA elastic buffer becomes full at the same time as a beacon is being transmitted, the beacon is properly transmitted. However, the device will exhibit the following deviations from expected behavior:
  1. In RMII mode, the coordinator will ignore received packets after the transmitted beacon until the device's next valid transmit opportunity.
  2. In MII mode, the COL pin of the coordinator may exhibit a short de-assertion pulse during a logical collision coincident with the transmission of a beacon.
Due to the size of the internal elastic buffer, these deviations can only happen on mixing segments with more than 11 idle transmit opportunities in a row.

End User Implications

In a system where more than 11 idle transmit opportunities occur in a row, there is a small possibility that a transmitted packet will fill the elastic buffer FIFO at exactly the time that the transmit opportunity starts in the node. Should this happen, the fault behaviors above will have the following consequences:
  1. The MAC will react to the early de-assertion of carrier sense and attempt to re-transmit the packet earlier than it should following a logical collision. If the MAC retry timing is such that the FIFO becomes full at the start of the transmit opportunity, the packet latency will increase as the MAC will use the exponential back off algorithm to determine when to retry transmission. Should retries continue to occur for a single packet, the exponential back off will continue to increase. It is unlikely but possible that the packet may be dropped by the MAC due to excessive retries. In this case, the transmitter will fail to transmit the packet.
  2. It is theoretically possible that other devices on the mixing segment may detect a short carrier sense due to the transmitted ‘J’ symbol which could cause one packet to be delayed in transmission, however, there are no known devices which detect carrier based on a single 'J' symbol.
  3. An RMII coordinator may miss receiving packets.
  4. The brief de-assertion of the COL pin has not been shown to have any negative effects on MACs.

Work Around

This issue can only occur with more than 11 idle transmit opportunities in a row. This maximum number of transmit opportunities for a mixing segment is set by the NCNT bit field of the PLCA_CTRL1 register of the coordinator. If this bit field is set to 11 or less, this behavior will never occur.

A system in which the end application can tolerate an occasional delayed packet is called latency insensitive. Even when a system has 12 or more transmit opportunities, if it is latency insensitive there may be no need for a workaround.

When a system has 12 or more transmit opportunities, is latency sensitive, and the end application uses a packet numbering and a retry mechanism, such as used in TCP, there may be no need for a workaround.

If a latency sensitive system requires 12 or more transmit opportunities, traffic flows should be designed to avoid more than 11 sequential idle transmit opportunities. If a small number of devices are using most of the transmit bandwidth, burst mode should be avoided but the multiple node ID feature can be used to distribute the load so that there are no more than 11 idle transmit opportunities. A heart-beat safety mechanism, as recommended in the safety manual, can also be used to keep nodes active.

Plan

This erratum will be corrected in an upcoming revision.