13.5.3 Interrupt Priority Level 0
| Name: | LVL0PRI |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LVL0PRI[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – LVL0PRI[7:0] Interrupt Priority Level 0
When Round Robin is enabled (the LVL0RR bit in CPUINT.CTRLA is '1'), this bit field stores the vector of the last acknowledged priority level 0 (LVL0) interrupt. The stored vector will have the lowest priority next time one or more LVL0 interrupts are pending.
If Round Robin is disabled (the LVL0RR bit in CPUINT.CTRLA is '0'), the vector address-based priority scheme (lowest address has the highest priority) is governing the priorities of LVL0 interrupt requests.
If a system Reset is asserted, the lowest interrupt vector address will have the highest priority within the LVL0.