20.7.5 Control Register E Clear - Split Mode

The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be cleared without the use of a read-modify-write operation on a single register.
Name: CTRLECLR
Offset: 0x04
Reset: 0x00
Property: -

Bit 76543210 
     CMD[1:0]CMDEN[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:2 – CMD[1:0] Command

These bits are used for software control of update, restart, and reset of the timer/counter. The command bits are always read as '0'.

ValueNameDescription
0x0 NONE No command
0x1 - Reserved
0x2 RESTART Force restart
0x3 RESET Force hard Reset (ignored if TC is enabled)

Bits 1:0 – CMDEN[1:0] Command enable

These bits are used to indicate for which timer/counter the command (CMD) is valid.

ValueNameDescription
0x0 NONE None
0x1 - Reserved
0x2 - Reserved
0x3 BOTH Command valid for both low-byte and high-byte T/C