All Signals Supported on Control, Write Data and Read Data Interfaces
Internal 5 AXI Ports Controller with Arbitration
External 16-bit DDR Interface
Support for 1 Memory Rank
For DDR3, LPDDR2 and LPDDR3 Configurations: Direct Software Request Control or Programmable Internal Control for ZQ Short Calibration Cycles
For DDR3, LPDDR2 and LPDDR3 Configurations: Support for ZQ Long Calibration after Self-refresh Exit
For LPDDR2 and LPDDR3 Configurations: Support for ZQ Reset Feature through Software
Dynamic Scheduling to Optimize Bandwidth and Latency
Read and Write Buffers in Fully Associative CAMs (Content Addressable Memories)
Delayed Writes for Optimum Performance on SDRAM Data Bus
Software-programmable Quality of Service (QoS) Support
Control Options to Avoid Starvation of Lower Priorities
Coherency for Write-After-Read (WAR) and Read-After-Write (RAW)
Hazards
Paging Policy Selectable by Configuration Registers:
Leave pages open after accesses, or
Close page when no further accesses are available in the controller for that page, or
Auto-precharge with each access, with an optimization for Page Close mode which leaves the page open after a flush for read-write and write-read collision cases
Supports Automatic DDR-SDRAM Power-down Entry and Exit caused by Lack of Incoming Transaction for a Programmable Time
Supports Automatic Clock Stop (LPDDR2/LPDDR3) Entry and Exit caused by
Lack of Incoming Transaction
Supports Automatic UDDRC Low-power Mode Operation caused by Lack of Transaction Arrival for a Programmable Time through the Hardware Low-power Interface
Supports Self-refresh Entry and Exit as follows:
Support for automatic self-refresh entry and exit caused by lack of incoming transaction for a programmable time
Support for self-refresh entry and exit under software control
Support for self-refresh entry and exit using dedicated DDRC hardware low-power interface control
Support for Dynamically Changing Clock Frequency while in Self-refresh:
DDR3 DLL-off mode supported
Shadow timing registers provided to allow fast frequency changing
Support for Deep Power-down Entry and Exit under Software Control
(LPDDR2/LPDDR3)
Support for explicit SDRAM Mode Register Updates under Software Control
Flexible Address Mapper Logic to allow Application-specific Mapping of Row, Column, Bank, and Rank Bits
Programmable Support for 1T or 2T Timing
User-selectable Refresh Control Options:
Controller-generated auto-refreshes at programmable average intervals
Ability to disable controller-generated auto-refreshes
Ability to issue a refresh through direct software request
When LPDDR2/LPDDR3 is used, user-selectable ability to perform per-bank refreshes rather than all-banks refreshes
Advanced Power-saving Design Includes No Unnecessary Toggling of
Command, Address, and Data Pins (RAS/CAS/WE/BA/A hold last state after each command;
DDR_D does not transition on writes when bytes are disabled)
Support for DDR2, DDR3, DDR3L, LPDDR2, LPDDR3
Leverages Out-of-order Requests to Maximize Throughout
The UDDRC Implements the Following Standards:
JEDEC DDR2 SDRAM Specification, JESD79-2
JEDEC DDR3 SDRAM Specification, JESD79-3
JEDEC DDR3L SDRAM Specification, JESD79-3-1A
JEDEC LPDDR2 SDRAM Specification, JESD209-2
JEDEC LPDDR3 SDRAM Specification, JESD209-3
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
