Up to 1-GHz Arm® Cortex®-A7, MIPI / LVDS Display, Dual Gigabit Ethernet, Audio and Security

Reference Document

1.2 Ordering Information

1.3 Product Identification System

1.5 Configuration Summary

1.6 Block Diagram

1.7 Signal Description

1.8 Package and Pinout

1.9 Microchip Recommended Power Management Solutions

1.10 Safety and Security Features

1.11 Memory Mapping

1.12 Peripheral Identifiers

2 CPU and Interconnect

2.1 Event System

2.2 System Interconnect and Security (SIS)

2.3 Cortex-A7 Processor (Arm)

2.4 External Interrupt Controller (EIC)

2.5 Debug and Test

2.6 NIC-400 Global Programmer’s View (NICGPV)

2.7 Bus Matrix (MATRIX)

2.8 DMA Controller (XDMAC)

2.9 Boot Strategies

3.2 Static Memory Controller (SMC)

3.3 Universal DDR Memory Controller (UDDRC)

3.4 DDR/LPDDR Physical Interface (DDR3PHY)

4 System Controller

4.2 System Controller Write Protection (SYSCWP)

4.3 General Purpose Backup Registers (GPBR)

4.4 Dual Watchdog Timer (DWDT)

4.5 Reset Controller (RSTC)

4.6 Real-Time Timer (RTT)

4.7 Real-Time Clock (RTC)

4.8 Shutdown Controller (SHDWC)

4.9 Boot Sequence Controller (BSC)

4.10 64-bit Periodic Interval Timer (PIT64B)

4.11 Chip Identifier (CHIPID)

4.12 OTP Memory Controller (OTPC)

4.13 Special Function Registers (SFR)

4.14 Special Function Registers Backup (SFRBU)

4.15 Slow Clock Controller (SCKC)

4.16 Clock Generator

4.17 Power Management Controller (PMC)

4.18 Parallel Input/Output Controller (PIO)

5 Analog Subsystem

5.2 Analog-to-Digital Converter (ADC) Controller

5.3 Analog Comparator Controller (ACC)

6 Image Subsystem

6.2 LCD Controller (LCDC)

6.3 Low Voltage Differential Signaling Controller (LVDSC)

6.4 Display Serial Interface (DSI)

6.5 GPU2D Controller (GPU2DC)

7 Audio Subsystem

7.2 Inter-IC Sound Multi-Channel Controller (I2SMCC)

7.3 Synchronous Serial Controller (SSC)

7.4 Sony/Philips Digital Interface Receiver (SPDIFRX)

7.5 Sony/Philips Digital Interface Transmitter (SPDIFTX)

7.6 Pulse Density Microphone Controller (PDMC)

7.7 Asynchronous Sample Rate Converter (ASRC)

8 Security and Cryptography Subsystem

8.2 TrustZone Advanced Encryption Standard Bridge (TZAESB)

8.3 TrustZone AES Bridge Address Space Controller (TZAESBASC)

8.4 TrustZone Address Space Controller (TZC)

8.5 TrustZone Peripheral Manager (TZPM)

8.6 Advanced Encryption Standard (AES)

8.7 Secure Hash Algorithm (SHA)

8.8 Triple Data Encryption Standard (TDES)

8.9 Random Number Generator (TRNG)

8.10 Integrity Check Monitor (ICM)

8.11 Classical Public Key Cryptography Controller (CPKCC)

8.12 Security Module (SECUMOD)

8.13 Physical Unclonable Functions (PUF)

9 Connectivity Subsystem

9.2 Ethernet MAC (GMAC)

9.3 Flexible Serial Communication Controller (FLEXCOM)

9.4 Quad Serial Peripheral Interface (QSPI)

9.5 Secure Digital MultiMedia Card Controller (SDMMC)

9.6 Controller Area Network (MCAN)

9.7 I3C Controller (I3CC)

9.8 Pulse Width Modulation Controller (PWM)

9.9 Timer Counter (TC)

10 USB Subsystem

10.2 USB Type-C™ Port Controller (TCPC)

10.3 USB Device High Speed Port (UDPHS)

10.4 USB Host High Speed Port (UHPHS)

11 Electrical and Mechanical Characteristics

11.1 Electrical Characteristics

11.2 Mechanical Characteristics

13 Revision History

13.1 Revision History

Microchip Information

Microchip Devices Code Protection Feature

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