5.2.6.4 ADC Channel Sequence Register 2

This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register.

Name:	ADC_SEQR2
Offset:	0x0C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	USCH16[3:0]				USCH15[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	USCH14[3:0]				USCH13[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	USCH12[3:0]				USCH11[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	USCH10[3:0]				USCH9[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0:3, 4:7, 8:11, 12:15, 16:19, 20:23, 24:27, 28:31 – USCHx User Sequence Number x

The allowed range is 0 to 15, thus only a CH0 to CH15 sequence can be used.

This register can be used only if ADC_MR.USEQ is set to ‘1’.

Any USCHx field is processed only if the CHx-1 bit in ADC_CHSR reads logical ‘1’, else any value written in USCHx does not add the corresponding channel in the conversion sequence.

Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs.