Compliant with Inter-IC Sound (I2S) Bus Specification
Host, Client, and Controller Modes
Client: Data received/transmitted
Host: Data received/transmitted and clocks generated
Controller: Clocks generated
Independent Physical Link Samples Size
versus Audio File Samples Size
Software post/pre-processing on
audio file payload is not required
FIFO
Individual Enable and Disable of Receiver, Transmitter and Clocks
Configurable Clock Generator Common to Receiver and Transmitter
Suitable for a wide range of sample frequencies (fs), including 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96
kHz, and 192 kHz
16 fs to 1024 fs host clock generated for external oversampling data converters
Support for Multiple Data Formats
32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format
16- and 8-bit compact stereo format, with left and right samples
packed in the same word to reduce data transfers
Compact 24-bit support for optimized
system memory files and audio file generation and reading
Supports left-justification of 24-bit
audio samples in 32-bit audio file container
Support for Multiple Data Frame Formats
2-channel I2S with word select
1- to 8-channel Time Division Multiplexed (TDM) with frame
synchronization
Direct Audio Access from/to the
Asynchronous Sample Rate Converter (ASRC)
No loss of system bus bandwidth,
no data buffer in system memory, no DMA required for transfer
DMA Controller Interfaces the Receiver
and Transmitter to Reduce Processor Overhead
Smart Holding Registers Management to Avoid Audio Channel Mix After
Overrun or Underrun
Functional Safety Monitors and
Reports
Reinforced safety for some sensitive
configuration registers and single error correction
Parity monitoring for Mode
registers
Internal sequencer integrity check
reports
Abnormal software access reports
(undefined, write a read-only, read a write-only)
Register write protection
I2SMCC_WS and I2SMCC_CK output pad
integrity monitoring in Host mode
Fault Injection Capability
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