Data Width Configurable to 24 bits, 20 bits or 16 bits
Packed and Unpacked Data Support for System Memory Optimization
Line State Events Report and Source of Interrupt
Full Memory Map of 192 bits for Channel 1 and Channel 2 Status and
User Data
First 32-bit Status A, Status B Change Report and Source of Interrupt
Line Digital Filter
Direct Audio Access from/to the
Asynchronous Sample Rate Converter (ASRC)
No loss of system bus bandwidth, no data buffer in system memory, no DMA required
for transfer
Functional Safety Monitors and Reports
Reinforced safety for sensitive
configuration registers and single error correction
Parity monitoring for configuration
registers
Internal sequencer integrity check reports
Abnormal software access reports
(undefined, write a read-only, read a write-only)
Register Write Protection
Fault Injection Capability
Loop Test Mode (SPDIFTX drives SPDIFRX
internally)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
