Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications
Contains an Independent Receiver and Transmitter and a Common Clock Divider
Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead
Offers a Configurable Frame Sync and Data Length
Receiver and Transmitter can be Programmed to Start
Automatically or on Detection of Different Events on the Frame Sync Signal
Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Sync Signal
Up to 16 Channels in TDM Mode
8 Data Transmit FIFO
8 Data Receive FIFO
Direct Access from/to Asynchronous Sample
Rate Converter (ASRC)
No loss of system bus bandwidth, no data buffer in system memory, no DMA required
for transfer
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