3.1.3.1 Clocks

Memory clocks are not controlled by the PMC.

  • ROM and CPKCC are on the CPU System and Security (CSS) matrix and therefore clocked by MCK0.
  • SECURAM is located on CSS and clocked by MCK0 divided by 32.
  • SRAM, SMC and NFC_RAM are located on the AHB System (HSS) matrix, clocked by MCK5.
  • UDDRC and DDR3PHY are clocked as:
    • UDDRC and DDR3PHY core clocks are hard-wired to DDRPLLCK.
    • UDDRC and DDR3PHY APB configuration ports are clocked by MCK2.
    • These clocks must respect the following conditions: Freq(MCK2) ≤ 133 MHz and Freq(DDRPLLCK)/20 ≤ Freq(MCK2) ≤ Freq(DDRPLLCK)/2.
Note: The MCK0 frequency is directly related to the CPU clock, so any change on the CPU clock impacts MCK0.