4.4.4.8 Watchdog Halt
While the processor is in Debug state or in Sleep mode (including ULP1 mode), the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in PSWDT_MR or NSWDT_MR.
While the processor is in Debug state or in Sleep mode (including ULP1 mode), the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in PSWDT_MR or NSWDT_MR.
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