9.8.2 Embedded Characteristics

  • 4 Channels
  • Common Clock Generator Providing Thirteen Different Clocks
    • A Modulo n counter providing eleven clocks
    • Two independent linear dividers working on Modulo n counter outputs
  • Independent Channels
    • Independent 16-bit counter for each channel
    • Independent complementary outputs with 12-bit dead-time generator (also called dead-band or non-overlapping time) for each channel
    • Independent Push-Pull mode for each channel
    • Independent enable-disable command for each channel
    • Independent clock selection for each channel
    • Independent period, duty-cycle and dead-time for each channel
    • Independent double buffering of period, duty-cycle and dead-times for each channel
    • Independent programmable selection of the output waveform polarity for each channel, with double buffering
    • Independent programmable center- or left-aligned output waveform for each channel
    • Independent output override for each channel
    • Independent interrupt for each channel, at each period for left-aligned or center-aligned configuration
    • Independent update time selection of double buffering registers (polarity, duty cycle) for each channel, at each period for left-aligned or center-aligned configuration
  • External Trigger Input Management (e.g., for DC/DC or Lighting Control)
    • External PWM Reset mode
    • External PWM Start mode
    • Cycle-by-cycle duty cycle mode
    • Leading-edge blanking
  • 2 2-bit Gray Up/Down Channels for Stepper Motor Control
  • Spread Spectrum Counter to Allow a Constantly Varying Duty Cycle (only for Channel 0)
  • Synchronous Channel Mode
    • Synchronous channels share the same counter
    • Mode to update the synchronous channels registers after a programmable number of periods
    • Synchronous channels support connection of one DMA Controller channel offers buffer transfer without processor intervention to update duty-cycle registers
  • 2 Independent Event Lines Intended to Synchronize ADC Conversions
    • Programmable delay for event lines to delay ADC measurements
  • 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines and DMA Controller Transfer Requests
  • 5 Programmable Fault Inputs Providing Asynchronous Protection of PWM Outputs
    • Two driven by the user through PIO inputs
    • Driven by the PMC when crystal oscillator clock fails
    • Driven by the ADC Controller through configurable comparison function
    • Driven by the Timer/Counter through configurable comparison function
  • Register Write Protection