CSSYS Block (Debug and Trace Subsystem from SoC-400)
DAP with an asynchronous bridge to
allow DAP/CPU asynchronous clock
CXAPBIC APB interconnect
containing the top-level ROM table
ETB (Embedded Trace Buffer +
16-Kbyte ETB RAM)
Timestamp generation
component
ECT (Embedded Cross-Triggering)
component
Chip ID Register
IEEE 1149.1 JTAG Boundary-scan on All Digital Pins
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