2.8.8 XDMAC Software Requirements

Write operations to channel registers are not be performed in an active channel after the channel is enabled. If any channel parameters must be reprogrammed, this can only be done after disabling the XDMAC channel.

XDMAC_CSAx and XDMAC_CDAx channel registers must be programmed with a byte, half-word, word or double-word aligned address depending on the Channel x Data Width field (DWIDTH) of the XDMAC Channel x Configuration Register. When a memory-to-peripheral transfer is performed, the XDMAC_CSAx address register has no alignment requirement.

When a memory-to-memory transfer is performed, configure the field XDMAC_CCx.PERID (where ‘x’ is the index of the channel used for the transfer) to peripheral ID 127 (refer to the table “Peripheral Identifiers”).

When XDMAC_CC.INITD is set to 0, XDMAC_CUBC.UBLEN and XDMAC_CNDA.NDA field values are unreliable when the descriptor is being updated. The following procedure applies to get the buffer descriptor identifier and the residual bytes:

Read XDMAC_CNDAx.NDA(nda0)
Read XDMAC_CCx.INITD(initd0)
Read XDMAC_CCx.INITD(initd0)
Read XDMAC_CUBCx.UBLEN(ublen) 
Read XDMAC_CCx.INITD(initd1)
Read XDMA_CNDAx.NDA(nda1) 
If (nda0 == nda1 && initd0 == 1 && initd1 == 1).
Then the ublen is correct, the buffer id is nda.
Else retry

See the figure below.

Each DMA channel can be configured in either Secure or Non-secure mode independently. When a DMA channel is secure, its related global register fields and its channel registers cannot be modified nor read by non-secure software. Such non-secure reads return zero.

Non-secure channel bus error events can be rerouted to the Global Bus Error Interrupt Status register (XDMAC_GBEIS) instead of being flagged into the non-secure Channel Interrupt Status register (XDMAC_CIS). For this rerouting to take effect, the secure software has to write into the Global Bus Error Interrupt Routing register (XDMAC_GBEIR). When a non-secure channel GBEIS bit is set by a bus error, the corresponding channel Global Interrupt Status register (XDMAC_GIS) bit is also set and the DMA secure interrupt line is asserted until XDMAC_GBEIS is read by the secure software. This GBEIS effect on the GIS register and on the secure interrupt line cannot be masked. For the channels configured in Secure mode, the GBEIR bits are ignored and have no effect.