9.3.7.14.2 Monitors and Reports
When register write protection is enabled, any incorrect access is reported in FLEX_US_WPSR.WPVS and in FLEX_US_CSR.SECE. It is possible to trigger an interrupt by writing a 1 in FLEX_US_IER.SECE.
The UART protocol embeds a parity bit that can be used to detect erroneous transfers on the line but this method does not detect totally stuck-at outputs and a timeout function is required at the receiver. The timeout procedure may take a long time to report an abnormal transfer back to the emitter when considering the Open Systems Interconnection (OSI) model due to its location in higher layers. USART embeds an on-the-fly output monitoring to speed-up detection and report. The monitor cannot be disabled for safety reasons and only reports an error in the user interface (i.e. there is no action on the transmission path).
The monitor not only detects PAD transistor failure and external short-circuits but also hardware or software errors located in the IO multiplexing logic. These errors may arise from software configuration error or transistor failure. As example, a badly re-assigned TXD IO pin (software error) is detected as soon as the USART starts transmitting a character because it is unlikely for another peripheral sharing the same IO pin to drive the same waveform as the USART on TXD output.
In Asynchronous mode, the TXD output is monitored and if two successive bit periods show a difference between the internal output of the USART and the feedback from the TXD pad, an error is reported in FLEX_US_WPSR.PADERR and in FLEX_US_CSR.SECE. It is possible to trigger an interrupt by writing a 1 in FLEX_US_IER.SECE.
When the USART is configured in Synchronous mode (FLEX_US_MR.SYNC=1) and the SCK is driven by USART (FLEX_US_MR.CLKO=1), the serial clock SCK is also monitored while a character is being transmitted. An error is reported in FLEX_US_WPSR.PADERR and in FLEX_US_CSR.SECE if the number of clock edges at the SCK pad output is below 6 and greater or equal to 14 which addresses all the possible configurations (5 to 9 bits for data length, parity or no parity bit, 1 or 2 stop bits). Due to potential high speed transfer when synchronous mode is configured, the TXD is only checked to not be locked at logical 1 or 0 during a character transfer (the monitor expects a falling edge on TXD output corresponding to the beginning of start bit period).
The detection method minimizes the likelihood to report a false positive that could result for example from a single upset event.
The monitor covers any failure that would be located in the FLEXCOM IO multiplexing downstream circuitry, test logic, output pad buffer and external transmission line from the output pad to any buffering circuitry (if discrete components are placed between the transmitter and far-end receiver).