7.7.6.14 ASRC Error Status Register
| Name: | ASRC_ESR |
| Offset: | 0xA8 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DAOERR3 | DAOERR2 | DAOERR1 | DAOERR0 | DAIERR3 | DAIERR2 | DAIERR1 | DAIERR0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OTRIGERR | ITRIGERR | DARHXERR | DATHXERR | DAPSELOREDERR | DAPSELIREDERR | DAPSELOMAXERR | DAPSELIMAXERR | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DERR | OUTCFGERR[4:0] | ||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ROMS | SRAMS | INCFGERR[4:0] | |||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 28, 29, 30, 31 – DAOERRx Direct Access Output Transfer Error Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No error detected in the direct access link with audio peripherals receiving data from ASRC. |
| 1 | A data is missing in the direct access transfer between two synchronization events (ASRC trigger events). This may be due to a bad configuration of the audio peripheral receiving the data (for example, direct access is disabled or a hardware failure). |
Bits 24, 25, 26, 27 – DAIERRx Direct Access Input Transfer Error Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No error detected in the direct access link with audio peripherals providing data to ASRC. |
| 1 | A data is missing in the direct access transfer between two synchronization events (ASRC trigger events). This may be due to a bad configuration of the audio peripheral transmitting the data (for example, direct access is disabled or a hardware failure) or the ASRC direct access enable for channel x is disabled whereas a synchronization event is valid on the direct access physical link (the audio peripheral transmitting the data is enabled and a data has been already transmitted). The error may also rise if the ASRC direct access is being disabled when there is data pending on the direct access link. |
Bit 23 – OTRIGERR Output Trigger Configuration Error
| Value | Description |
|---|---|
| 0 | Validates the configuration of ASRC_TRIG.TRIGSELOUTx versus ASRC_CH_CONF.RHROPMODE. |
| 1 | The configuration of ASRC_TRIG.TRIGSELOUTx is incompatible with the configuration of ASRC_CH_CONF.RHROPMODE. The error is only reported when 1 DSP is enabled (ASRC_MR.ASRCENx differs from 0). The error is cleared when the configuration is correct. |
Bit 22 – ITRIGERR Input Trigger Configuration Error
| Value | Description |
|---|---|
| 0 | Validates the configuration of ASRC_TRIG.TRIGSELINx versus ASRC_CH_CONF.THROPMODE. |
| 1 | The configuration of ASRC_TRIG.TRIGSELINx is incompatible with the configuration of ASRC_CH_CONF.THROPMODE. The error is only reported when 1 DSP is enabled (ASRC_MR.ASRCENx differs from 0). The error is cleared when the configuration is correct. |
Bit 21 – DARHXERR Direct Access DARHM/DARHRx Configuration Error
| Value | Description |
|---|---|
| 0 | Validates the configuration of ASRC_MR.DARHM/DARHRx. |
| 1 | The configuration of ASRC_MR.DARHM/DARHRx is incompatible with the configuration of ASRC_CH_CONF.RHROPMODE. The error is only reported when 1 DSP is enabled (ASRC_MR.ASRCENx differs from 0). The error is cleared when the configuration is correct. |
Bit 20 – DATHXERR Direct Access DATHM/DATHRx Configuration Error
| Value | Description |
|---|---|
| 0 | Validates the configuration of ASRC_MR.DATHM/DATHRx. |
| 1 | The configuration of ASRC_MR.DATHM/DATHRx is incompatible with the configuration of ASRC_CH_CONF.THROPMODE. The error is only reported when 1 DSP is enabled (ASRC_MR.ASRCENx differs from 0). The error is cleared when the configuration is correct. |
Bit 19 – DAPSELOREDERR Direct Access Output Peripheral Selection Redundancy Configuration Error
| Value | Description |
|---|---|
| 0 | Validates the configuration of ASRC_DAPSELR.OUT_CHx and ASRC_MR.DARHRx. |
| 1 | The same audio peripheral is enabled to transmit data into more than one direct access channel. The ASRC_DAPSELR.OUT_CHx and ASRC_MR.DARHRx must be correctly configured to clear the error. |
Bit 18 – DAPSELIREDERR Direct Access Input Peripheral Selection Redundancy Configuration Error
| Value | Description |
|---|---|
| 0 | Validates the configuration of ASRC_DAPSELR.IN_CHx and ASRC_MR.DATHRx. |
| 1 | The same audio peripheral is enabled to receive data into more than one direct access channel. The ASRC_DAPSELR.IN_CHx and ASRC_MR.DATHRx must be correctly configured to clear the error. |
Bit 17 – DAPSELOMAXERR Direct Access Output Peripheral Selection Configuration Error on Maximum Values
| Value | Description |
|---|---|
| 0 | None of the values in ASRC_DAPSELR.OUT_CHx fields overpass the maximum number of audio peripherals allowed to transfer data directly from the ASRC or the related direct access receive channel is disabled in ASRC_MR.DARHRx. |
| 1 | One of the values in ASRC_DAPSELR.OUT_CHx fields overpass the maximum number of audio peripherals allowed to transfer data directly from the ASRC and the related direct access receive channel is enabled in ASRC_MR.DARHRx. The error is cleared when the configuration is correct. |
Bit 16 – DAPSELIMAXERR Direct Access Input Peripheral Selection Configuration Error on Maximum Values
| Value | Description |
|---|---|
| 0 | None of the values in ASRC_DAPSELR.IN_CHx fields overpass the maximum number of audio peripherals allowed to transfer data directly to the ASRC or the related direct access transmit channel is disabled in ASRC_MR.DATHRx. |
| 1 | One of the values in ASRC_DAPSELR.IN_CHx fields overpass the maximum number of audio peripherals allowed to transfer data directly to the ASRC and the related direct access transmit channel is enabled in ASRC_MR.DATHRx. The error is cleared when the configuration is correct. |
Bit 15 – DERR DSP Overflow Error
| Value | Description |
|---|---|
| 0 | No DSP overflow error detected. |
| 1 | The sampling frequency overpasses the value allowed by the configuration. |
Bits 12:8 – OUTCFGERR[4:0] Output Configuration Error
| Value | Name | Description |
|---|---|---|
| 0 | OUTCFG_OK | Correct configuration of ASRC_MR, ASRC_VBPS_OUT, ASRC_CH_CONF. |
| 1 | OP0_D0_CHK16_8M | Channel operating mode 0, DSP0: CHUNK0=16 or CHUNK0=8 and MONO0=1 is not supported. |
| 2 | OP0_D1_CHK16_8M | Channel operating mode 0, DSP1: CHUNK1=16 or CHUNK1=8 and MONO1=1 is not supported. |
| 3 | OP0_D2_CHK16_8M | Channel operating mode 0, DSP2: CHUNK2=16 or CHUNK2=8 and MONO2=1 is not supported. |
| 4 | OP0_D3_CHK16_8M | Channel operating mode 0, DSP3: CHUNK3=16 or CHUNK3=8 and MONO3=1 is not supported. |
| 5 | OP1_D01_EN | Channel operating mode 1, DSP0/1: enable configuration is not correct (1 DSP is disabled) |
| 6 | OP1_D01_M | Channel operating mode 1, DSP0/1: MONO0=1, MONO1=0 is not supported. |
| 7 | OP1_D01_CHK16 | Channel operating mode 1, DSP0/1: CHUNK0=16 is not supported. |
| 8 | OP1_D2_CHK16_8M | Channel operating mode 1, DSP2: CHUNK2=16 or CHUNK2=8 and MONO2=1 is not supported. |
| 9 | OP1_D3_CHK16_8M | Channel operating mode 1, DSP3: CHUNK3=16 or CHUNK3=8 and MONO3=1 is not supported. |
| 10 | OP2_D01_EN | Channel operating mode 2, DSP0/1: enable configuration is not correct (1 DSP is disabled) |
| 11 | OP2_D01_M | Channel operating mode 2, DSP0/1: MONO0=1, MONO1=0 is not supported. |
| 12 | OP2_D01_CHK16 | Channel operating mode 2, DSP0/1: CHUNK0=16 is not supported. |
| 13 | OP2_D23_EN | Channel operating mode 2, DSP2/3: enable configuration is not correct (1 DSP is disabled) |
| 14 | OP2_D23_M | Channel operating mode 2, DSP2/3: MONO2=1, MONO3=0 is not supported. |
| 15 | OP2_D23_CHK16 | Channel operating mode 2, DSP2/3: CHUNK2=16 is not supported. |
| 16 | OP3_D012_EN | Channel operating mode 3, DSP0/1/2: enable configuration is not correct (at least 1 DSP is disabled) |
| 17 | OP3_D012_M | Channel operating mode 3, DSP0/1/2: mono configuration is not correct (e.g. MONO0=1, MONO1=0 or MONO2=0 is not supported). |
| 18 | OP3_D012_CHK16 | Channel operating mode 3, DSP0/1/2: CHUNK0=16 is not supported. |
| 19 | OP3_D3_CHK16_8M | Channel operating mode 3, DSP3: CHUNK3=16 or CHUNK3=8 and MONO3 is not supported. |
| 20 | OP4_D0123_EN | Channel operating mode 4, DSP0/1/2/3: enable configuration is not correct (at least 1 DSP is disabled) |
| 21 | OP4_D0123_M | Channel operating mode 4, DSP0/1/2/3: mono configuration is not correct (e.g. MONO0=1, MONO1=0 or MONO2=0 or MONO3=0 is not supported). |
Bit 7 – ROMS DSP ROM Memory Check Status
| Value | Description |
|---|---|
| 0 | No error detected in the embedded memory when the check period is completed. When testing the ability for ROMS to rise by writing ASRC_FIR.F0=1, the clear is performed by first clearing ASRC_FIR.F0 followed by an additional read of the ASRC_WPSR to clear ASRC_ISRx.SECE, then restarting a memory check period again. When a permanent memory hardware failure exists, there is no way to clear this flag. |
| 1 | The embedded ROM memory contains a failure (check done with a CRC24, polynomial: 0x864CFB). This flag is cleared at the start of any memory check procedure. |
Bit 6 – SRAMS DSP SRAM Memory Check Status
| Value | Description |
|---|---|
| 0 | No error detected in the embedded memory when the check period is completed. When testing the ability for SRAMS to rise by writing ASRC_FIR.F0=1, the clear is performed by first clearing ASRC_FIR.F0 followed by an additional read of the ASRC_WPSR to clear ASRC_ISRx.SECE, then restarting a memory check period again. When a permanent memory hardware failure exists for a selected channel, it is possible to clear this flag by starting the memory check for another channel where memories does not embed permanent hardware failure. |
| 1 | One of the embedded RAM memories contains a failure. When ASRC_MR.DSPMEMSEL=0, one of the RAMs fails. ASRC_MR.DSPMEMSEL must be configured successively with values greater than 0 to determine the affected channel/DSP. This flag is cleared at the start of any memory check procedure. |
Bits 4:0 – INCFGERR[4:0] Input Configuration Error
| Value | Name | Description |
|---|---|---|
| 0 | OUTCFG_OK | Correct configuration of ASRC_MR, ASRC_VBPS_OUT, ASRC_CH_CONF. |
| 1 | OP0_D0_CHK16_8M | Channel operating mode 0, DSP0: CHUNK0=16 or CHUNK0=8 and MONO0=1 is not supported. |
| 2 | OP0_D1_CHK16_8M | Channel operating mode 0, DSP1: CHUNK1=16 or CHUNK1=8 and MONO1=1 is not supported. |
| 3 | OP0_D2_CHK16_8M | Channel operating mode 0, DSP2: CHUNK2=16 or CHUNK2=8 and MONO2=1 is not supported. |
| 4 | OP0_D3_CHK16_8M | Channel operating mode 0, DSP3: CHUNK3=16 or CHUNK3=8 and MONO3=1 is not supported. |
| 5 | OP1_D01_EN | Channel operating mode 1, DSP0/1: enable configuration is not correct (1 DSP is disabled) |
| 6 | OP1_D01_M | Channel operating mode 1, DSP0/1: MONO0=1, MONO1=0 is not supported. |
| 7 | OP1_D01_CHK16 | Channel operating mode 1, DSP0/1: CHUNK0=16 is not supported. |
| 8 | OP1_D2_CHK16_8M | Channel operating mode 1, DSP2: CHUNK2=16 or CHUNK2=8 and MONO2=1 is not supported. |
| 9 | OP1_D3_CHK16_8M | Channel operating mode 1, DSP3: CHUNK3=16 or CHUNK3=8 and MONO3=1 is not supported. |
| 10 | OP2_D01_EN | Channel operating mode 2, DSP0/1: enable configuration is not correct (1 DSP is disabled) |
| 11 | OP2_D01_M | Channel operating mode 2, DSP0/1: MONO0=1, MONO1=0 is not supported. |
| 12 | OP2_D01_CHK16 | Channel operating mode 2, DSP0/1: CHUNK0=16 is not supported. |
| 13 | OP2_D23_EN | Channel operating mode 2, DSP2/3: enable configuration is not correct (1 DSP is disabled) |
| 14 | OP2_D23_M | Channel operating mode 2, DSP2/3: MONO2=1, MONO3=0 is not supported. |
| 15 | OP2_D23_CHK16 | Channel operating mode 2, DSP2/3: CHUNK2=16 is not supported. |
| 16 | OP3_D012_EN | Channel operating mode 3, DSP0/1/2: enable configuration is not correct (at least 1 DSP is disabled) |
| 17 | OP3_D012_M | Channel operating mode 3, DSP0/1/2: mono configuration is not correct (e.g. MONO0=1, MONO1=0 or MONO2=0 is not supported). |
| 18 | OP3_D012_CHK16 | Channel operating mode 3, DSP0/1/2: CHUNK0=16 is not supported. |
| 19 | OP3_D3_CHK16_8M | Channel operating mode 3, DSP3: CHUNK3=16 or CHUNK3=8 and MONO3 is not supported. |
| 20 | OP4_D0123_EN | Channel operating mode 4, DSP0/1/2/3: enable configuration is not correct (at least 1 DSP is disabled) |
| 21 | OP4_D0123_M | Channel operating mode 4, DSP0/1/2/3: mono configuration is not correct (e.g. MONO0=1, MONO1=0 or MONO2=0 or MONO3=0 is not supported). |