| 32 | Safety and Security Configuration registers |
| 33 | LCDC Configuration registers block 1 (peripheral clock
domain) |
| 34 | LCDC Configuration registers block 2 (peripheral clock
domain) |
| 57 | Attribute Management registers (peripheral clock domain) |
| 128 | Safety Management Attribute registers block 1 |
| 129 | Safety Management Attribute registers block 2 |
| 130 | Safety Management Attribute registers block 3 |
| 131 | Base Layer Attribute registers block 1 |
| 133 | Overlay 1 Attribute registers block 1 |
| 139 | High-End Overlay Attribute registers block 1 |
| 192 | LCDC Configuration registers block 1 (source clock domain) |
| 193 | LCDC Configuration registers block 2 (source clock domain) |
| 194 | LCDC Configuration registers block 3 (source clock domain) |
| 195 | LCDC Configuration registers block 4(source clock domain) |
| 196 | LCDC Critical Finite-State Machines block 1 |
| 197 | LCDC Critical Finite-State Machines block 2 |
