9.3.8.9.2 Monitors and Reports
When register write protection is enabled, any incorrect access is reported in FLEX_SPI_WPSR.WPVS and in FLEX_SPI_CSR.SECE. It is possible to trigger an interrupt by writing a 1 in FLEX_SPI_IER.SECE.
The SPI transfer high level protocols may include some characters acting as CRC to detect erroneous transfers on the line but this method does not detect totally stuck-at fault outputs. Moreover, it provides a longer response time when considering the Open Systems Interconnection (OSI) model due to its location in higher layers. A timeout function can be added at the device level to detect stuck-at faults. The timeout procedure may also take a long time to report an abnormal transfer back to the host because only high layer software stacks can manage this action. SPI embeds an on-the-fly output monitoring to speed-up detection and report. The monitor cannot be disabled for safety reasons and only reports an error in the user interface (i.e. there is no action on the transmission path).
Some output pad values are monitored when the transmitter is enabled and a character is being transmitted. The SPI internal outputs are passed through IO multiplexing logic that may be unintentionally badly configured and leads to absence or bad transmission. Other causes of stuck-at can be detected (external cause such as short-circuits or internal cause such as pad buffer transistor failure). For example, a badly re-assigned MOSI IO pin (software error) is detected as soon as the SPI starts transmitting a character because it is unlikely for another peripheral sharing the same IO pin to drive the same waveform as the SPI on MOSI output.
When the SPI is configured in Host mode (FLEX_SPI_MR.MSTR=1), the NPCS0, MOSI and SPCK pad outputs are monitored when a character is being transmitted. An error is reported in FLEX_SPI_WPSR.PADERR and in FLEX_SPI_SR.SECE. It is possible to trigger an interrupt by writing a 1 in FLEX_SPI_IER.SECE. Due to potential high speed transfer with SPI and SPI protocol not embedding any frame control bit in the data, the MOSI is only checked when FLEX_SPI_MR.MLCE=1. When the SPCK clock frequency is higher than 1 MHz, FLEX_SPI_MR.MLCE must be cleared. When FLEX_SPI_MR.MLCE=1, all bits are checked during the transmission of a character.
The detection method minimizes the likelihood to report a false positive that could result for example from a single upset event.
The monitor covers any failure that is located in the FLEXCOM IO multiplexing downstream circuitry, test logic, output pad buffer and external transmission line from the output pad to any buffering circuitry (if discrete components are placed between the transmitter and far-end receiver).