3.3.5.14.4 Power Removal Flow

Table 3-24. Power Removal
Step	Description	Comment
1	Write 0 to PCTRL_n.port_en	Blocks AXI ports from taking any more transactions
2	Poll PSTAT.rd_port_busy_n = 0 Poll PSTAT.wr_port_busy_n = 0	Waits unit all AXI ports are idle
3	Write 1 to PWRCTL.selfref_sw	Causes system to move to Self-refresh state
4	Poll STAT.selfref_type= 2’b10	Waits until Self-refresh state is entered
5	Place IOs in Retention mode	Refer to the section “DDR/LPDDR Physical Interface (DDR3PHY)”
6	Remove power	–

Table 3-25. Re-enabling the Power
Step	Description	Comment
1	Enable Power	–
2	Reset controller/PHY by driving core_ddrc_rstn = 1’b0, aresetn_n = 1’b0, presetn = ’b0	–
3	Remove APB reset, presetn =1’b1, and rereprogram the registers to pre-power removal values	–
4	Program INIT0.skip_dram_init = 2’b11	Skips the DRAM init routine and starts up in Self-refresh mode
5	Programs PWRCTL.selfref_sw = 1’b1	Keeps the controller in Self-refresh mode
6	Program DFIMISC.dfi_init_complete_en to 1’b0	PHY initialization needs to be rerun, so set to 0 until initialization complete
7	Remove the core reset core_ddrc_rstn = 1’b1 aresetn_n = 1’b1	–
8	Run PHY initialization/training as required, including removing the IOs from Retention mode	Refer to the section “DDR3PHY”
9	Program DFIMISC.dfi_init_complete_en to 1’b1	Indicates to controller that PHY has completed re-training/initialization
10	Program PWRCTL.selfref_sw = 1’b0	Triggers Self-refresh exit
11	Poll STAT.selfref_type = 2’b00	Wait until Self-refresh state is exited
12	Poll STAT.operating_mode for Normal mode entry	–
13	Write PCTRL.port_en = 1	AXI ports are no longer blocked from taking transactions